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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-29 16:30:33 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-14 13:45:49 +0000 |
| commit | fe8faa62b74087febe227f69385db3e562682799 (patch) | |
| tree | 2ae38f63d387a49c048f3dc9f71f07eb70bce1ce /src/arch/arm/types.hh | |
| parent | 831184d2949fbd790a2040738079ca03c8cfdefe (diff) | |
| download | gem5-fe8faa62b74087febe227f69385db3e562682799.tar.xz | |
arch-arm: Add Illegal Execution flag to PCState
This patch moves the detection of the Illegal Execution flag (PSTATE.IL)
from the tlb translation stage (fetch) to the decoding stage. This is
done by adding the illegalExecution field to the PCState.
Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10813
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/types.hh')
| -rw-r--r-- | src/arch/arm/types.hh | 27 |
1 files changed, 23 insertions, 4 deletions
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index 84887a1ca..07cdfadc8 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2013, 2017 ARM Limited + * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -70,6 +70,7 @@ namespace ArmISA BitUnion64(ExtMachInst) // Decoder state Bitfield<63, 62> decoderFault; // See DecoderFault + Bitfield<61> illegalExecution; // ITSTATE bits Bitfield<55, 48> itstate; @@ -218,14 +219,16 @@ namespace ArmISA JazelleBit = (1 << 1), AArch64Bit = (1 << 2) }; + uint8_t flags; uint8_t nextFlags; uint8_t _itstate; uint8_t _nextItstate; uint8_t _size; + bool _illegalExec; public: PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0), - _size(0) + _size(0), _illegalExec(false) {} void @@ -236,10 +239,22 @@ namespace ArmISA } PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), - _nextItstate(0), _size(0) + _nextItstate(0), _size(0), _illegalExec(false) { set(val); } bool + illegalExec() const + { + return _illegalExec; + } + + void + illegalExec(bool val) + { + _illegalExec = val; + } + + bool thumb() const { return flags & ThumbBit; @@ -472,7 +487,9 @@ namespace ArmISA { return Base::operator == (opc) && flags == opc.flags && nextFlags == opc.nextFlags && - _itstate == opc._itstate && _nextItstate == opc._nextItstate; + _itstate == opc._itstate && + _nextItstate == opc._nextItstate && + _illegalExec == opc._illegalExec; } bool @@ -490,6 +507,7 @@ namespace ArmISA SERIALIZE_SCALAR(nextFlags); SERIALIZE_SCALAR(_itstate); SERIALIZE_SCALAR(_nextItstate); + SERIALIZE_SCALAR(_illegalExec); } void @@ -501,6 +519,7 @@ namespace ArmISA UNSERIALIZE_SCALAR(nextFlags); UNSERIALIZE_SCALAR(_itstate); UNSERIALIZE_SCALAR(_nextItstate); + UNSERIALIZE_SCALAR(_illegalExec); } }; |