diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-26 10:21:20 -0500 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-26 10:21:20 -0500 |
commit | 608641e23c7f2288810c3f23a1a63790b664f2ab (patch) | |
tree | 0656aaf9653e8d263f5daac0d5f0fe3190193ae5 /src/arch/arm/utility.cc | |
parent | 6e354e82d9395b20f5f148cd545d0666b626e8ac (diff) | |
download | gem5-608641e23c7f2288810c3f23a1a63790b664f2ab.tar.xz |
cpu: implements vector registers
This adds a vector register type. The type is defined as a std::array of a
fixed number of uint64_ts. The isa_parser.py has been modified to parse vector
register operands and generate the required code. Different cpus have vector
register files now.
Diffstat (limited to 'src/arch/arm/utility.cc')
-rw-r--r-- | src/arch/arm/utility.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 34fcfd482..e1f9dfe04 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -156,6 +156,9 @@ copyRegs(ThreadContext *src, ThreadContext *dest) for (int i = 0; i < NumCCRegs; i++) dest->setCCReg(i, src->readCCReg(i)); + // Copy vector registers when vector registers put to use. + assert(NumVectorRegs == 0); + for (int i = 0; i < NumMiscRegs; i++) dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); |