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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-01-23 11:19:50 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-03-12 10:23:50 +0000 |
| commit | a2df8b2f631b82b2830a64206fe50acbf12e7940 (patch) | |
| tree | 4c12f75ace5c920b1acde5c0529670602c38f97d /src/arch/arm/utility.cc | |
| parent | b3d0f2d66a5bf79f66893adcb85b0ac78daf3f65 (diff) | |
| download | gem5-a2df8b2f631b82b2830a64206fe50acbf12e7940.tar.xz | |
arch-arm: Implement missing aarch32 TLBI registers
In the pool of TLB Invalidate system register a category of instruction
was missing: the ones operating on entries added to the TLB during the
last level only of a table walk. (E.g. TLBIVMAL). This patch is not
considering this matching criteria when invalidating the entries and it
is rather performing the invalidation on all levels.
Change-Id: I5f2186cfdd73793e76c90b260f7128be187903fe
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8821
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/utility.cc')
| -rw-r--r-- | src/arch/arm/utility.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 4e99d980e..c272ef624 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -464,6 +464,8 @@ mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, case MISCREG_TLBIMVAIS: case MISCREG_TLBIASIDIS: case MISCREG_TLBIMVAAIS: + case MISCREG_TLBIMVALIS: + case MISCREG_TLBIMVAALIS: case MISCREG_DTLBIALL: case MISCREG_ITLBIALL: case MISCREG_DTLBIMVA: @@ -473,6 +475,8 @@ mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, case MISCREG_TLBIMVAA: case MISCREG_TLBIALL: case MISCREG_TLBIMVA: + case MISCREG_TLBIMVAL: + case MISCREG_TLBIMVAAL: case MISCREG_TLBIASID: trapToHype = hcr.ttlb; break; |