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authorAli Saidi <Ali.Saidi@ARM.com>2010-11-15 14:04:03 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2010-11-15 14:04:03 -0600
commit4c2e5c282b334dcd263373c48d325c7f77847c61 (patch)
tree3139a60a9725b971ff26da6c0588f77a93bd0f0f /src/arch/arm/utility.cc
parent08c5673d56ddb77b3dd93d96b405c96c18c491d2 (diff)
downloadgem5-4c2e5c282b334dcd263373c48d325c7f77847c61.tar.xz
ARM: Add support for switching CPUs
Diffstat (limited to 'src/arch/arm/utility.cc')
-rw-r--r--src/arch/arm/utility.cc17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index a114ec5e0..c42a8dddd 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -133,5 +133,22 @@ skipFunction(ThreadContext *tc)
tc->pcState(newPC);
}
+void
+copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+ int i;
+ for(i = 0; i < TheISA::NumIntRegs; i++)
+ dest->setIntReg(i, src->readIntReg(i));
+ for(i = 0; i < TheISA::NumFloatRegs; i++)
+ dest->setFloatReg(i, src->readFloatReg(i));
+ for(i = 0; i < TheISA::NumMiscRegs; i++)
+ dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
+ // setMiscReg "with effect" will set the misc register mapping correctly.
+ // e.g. updateRegMap(val)
+ dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
+
+ // Lastly copy PC/NPC
+ dest->pcState(src->pcState());
+}
}