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author | Nathanael Premillieu <Nathanael.Premillieu@arm.com> | 2015-05-26 03:21:42 -0400 |
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committer | Nathanael Premillieu <Nathanael.Premillieu@arm.com> | 2015-05-26 03:21:42 -0400 |
commit | 31fd18ab156f86ec2fced0641d2c76fba60a7d2d (patch) | |
tree | 7f02bc701f3b3a85c702ebe1d0546e15ca42a17c /src/arch/arm/utility.cc | |
parent | 53a360985b5d298e03ed0102d750b2c362ec1d90 (diff) | |
download | gem5-31fd18ab156f86ec2fced0641d2c76fba60a7d2d.tar.xz |
arm: Make address translation faster with better caching
This patch adds better caching of the sys regs for AArch64, thus
avoiding unnecessary calls to tc->readMiscReg(MISCREG_CPSR) in the
non-faulting case.
Diffstat (limited to 'src/arch/arm/utility.cc')
-rw-r--r-- | src/arch/arm/utility.cc | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index e4a8f506f..34fcfd482 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -272,6 +272,38 @@ isBigEndian64(ThreadContext *tc) } Addr +purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, + TTBCR tcr) +{ + switch (el) { + case EL0: + case EL1: + if (bits(addr, 55, 48) == 0xFF && tcr.tbi1) + return addr | mask(63, 55); + else if (!bits(addr, 55, 48) && tcr.tbi0) + return bits(addr,55, 0); + break; + // @todo: uncomment this to enable Virtualization + // case EL2: + // assert(ArmSystem::haveVirtualization()); + // tcr = tc->readMiscReg(MISCREG_TCR_EL2); + // if (tcr.tbi) + // return addr & mask(56); + // break; + case EL3: + assert(ArmSystem::haveSecurity(tc)); + if (tcr.tbi) + return addr & mask(56); + break; + default: + panic("Invalid exception level"); + break; + } + + return addr; // Nothing to do if this is not a tagged address +} + +Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el) { TTBCR tcr; |