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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:03 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:03 -0600 |
| commit | 13931b9b827abd8a9fba5cb4448b69066746637c (patch) | |
| tree | 348231f50e7e0fd224fdf255b3c0a2159097750f /src/arch/arm/utility.cc | |
| parent | 4c2e5c282b334dcd263373c48d325c7f77847c61 (diff) | |
| download | gem5-13931b9b827abd8a9fba5cb4448b69066746637c.tar.xz | |
ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.
Diffstat (limited to 'src/arch/arm/utility.cc')
| -rw-r--r-- | src/arch/arm/utility.cc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index c42a8dddd..9293a4cfe 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -48,6 +48,8 @@ #include "mem/vport.hh" #endif +#include "arch/arm/tlb.hh" + namespace ArmISA { void @@ -148,7 +150,11 @@ copyRegs(ThreadContext *src, ThreadContext *dest) // e.g. updateRegMap(val) dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR)); - // Lastly copy PC/NPC + // Copy over the PC State dest->pcState(src->pcState()); + + // Invalidate the tlb misc register cache + dest->getITBPtr()->invalidateMiscReg(); + dest->getDTBPtr()->invalidateMiscReg(); } } |