diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-25 17:37:06 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-01 15:47:55 +0000 |
| commit | 30746da58f3dbcb37df6214999ad48cb7df1cc4a (patch) | |
| tree | 097ef94a83f7fc0d8bb60aec450b8322f6bee9cc /src/arch/arm/utility.cc | |
| parent | 312f44831f45c363bb1a97fdc601cb5efc8d5652 (diff) | |
| download | gem5-30746da58f3dbcb37df6214999ad48cb7df1cc4a.tar.xz | |
arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
This patch implements AArch64 Memory Model Feature Register 2
(from ARMv8.2)
Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/13066
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/utility.cc')
| -rw-r--r-- | src/arch/arm/utility.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index dec85ef65..e642250d8 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -750,6 +750,7 @@ msrMrs64TrapToHyp(const MiscRegIndex miscReg, case MISCREG_ID_AA64ISAR1_EL1: case MISCREG_ID_AA64MMFR0_EL1: case MISCREG_ID_AA64MMFR1_EL1: + case MISCREG_ID_AA64MMFR2_EL1: case MISCREG_ID_AA64AFR0_EL1: case MISCREG_ID_AA64AFR1_EL1: assert(isRead); |