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| author | Dylan Johnson <Dylan.Johnson@ARM.com> | 2016-08-02 10:38:03 +0100 |
|---|---|---|
| committer | Dylan Johnson <Dylan.Johnson@ARM.com> | 2016-08-02 10:38:03 +0100 |
| commit | 02fcca9b6ff8a6f8db06cbd3f897956bc218a544 (patch) | |
| tree | 0bcf738cccd9ab9646218498d741248216cd79c7 /src/arch/arm/utility.hh | |
| parent | c2271e301dc441944dfc4c19ac932ea4f926a863 (diff) | |
| download | gem5-02fcca9b6ff8a6f8db06cbd3f897956bc218a544.tar.xz | |
arm: Fix trapping to Hypervisor during MSR/MRS read/write
This patch restricts trapping to hypervisor only if we are in the
correct exception level for the trap to happen.
Change-Id: I0a382b6a572ef835ea36d2702b8a81b633bd3df0
Diffstat (limited to 'src/arch/arm/utility.hh')
| -rw-r--r-- | src/arch/arm/utility.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index 4b87dcc13..3a5a468dd 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -265,8 +265,8 @@ mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr, bool msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el, CPACR cpacr); -bool msrMrs64TrapToHyp(const MiscRegIndex miscReg, bool isRead, CPTR cptr, - HCR hcr, bool * isVfpNeon); +bool msrMrs64TrapToHyp(const MiscRegIndex miscReg, ExceptionLevel el, + bool isRead, CPTR cptr, HCR hcr, bool * isVfpNeon); bool msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr, ExceptionLevel el, bool * isVfpNeon); |