diff options
author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-02 13:38:30 +0100 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-02 13:38:30 +0100 |
commit | f48ad5b29d6f291b4f3679ff5fb7b5beae10d6fa (patch) | |
tree | d08e72f1eeeea81b33b60b6bd0f90f1cbd9f174d /src/arch/arm/utility.hh | |
parent | 53ae19bb5dce904915385515d87ff3c9a69ee170 (diff) | |
download | gem5-f48ad5b29d6f291b4f3679ff5fb7b5beae10d6fa.tar.xz |
arm: Correctly check FP/SIMD access permission in aarch32
The current implementation of aarch32 FP/SIMD in gem5 assumes that EL1
and higher are all 32-bit. This breaks interprocessing since an
aarch64 EL1 uses different enable/disable bits. This change updates
the permission checks to according to what is prescribed by the ARM
ARM.
Change-Id: Icdcef31b00644cfeebec00216b3993aa1de12b88
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Mitch Hayenga <mitch.hayenga@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Diffstat (limited to 'src/arch/arm/utility.hh')
-rw-r--r-- | src/arch/arm/utility.hh | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index 9268a0d5c..8fb6558be 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -260,20 +260,6 @@ bool msrMrs64TrapToHyp(const MiscRegIndex miscReg, bool isRead, CPTR cptr, bool msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr, ExceptionLevel el, bool * isVfpNeon); -bool -vfpNeonEnabled(uint32_t &seq, HCPTR hcptr, NSACR nsacr, CPACR cpacr, CPSR cpsr, - uint32_t &iss, bool &trap, ThreadContext *tc, - FPEXC fpexc = (1<<30), bool isSIMD = false); - -static inline bool -vfpNeon64Enabled(CPACR cpacr, ExceptionLevel el) -{ - if ((el == EL0 && cpacr.fpen != 0x3) || - (el == EL1 && !(cpacr.fpen & 0x1))) - return false; - return true; -} - bool SPAlignmentCheckEnabled(ThreadContext* tc); uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); |