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| author | Nathanael Premillieu <Nathanael.Premillieu@arm.com> | 2015-05-26 03:21:42 -0400 |
|---|---|---|
| committer | Nathanael Premillieu <Nathanael.Premillieu@arm.com> | 2015-05-26 03:21:42 -0400 |
| commit | 31fd18ab156f86ec2fced0641d2c76fba60a7d2d (patch) | |
| tree | 7f02bc701f3b3a85c702ebe1d0546e15ca42a17c /src/arch/arm/utility.hh | |
| parent | 53a360985b5d298e03ed0102d750b2c362ec1d90 (diff) | |
| download | gem5-31fd18ab156f86ec2fced0641d2c76fba60a7d2d.tar.xz | |
arm: Make address translation faster with better caching
This patch adds better caching of the sys regs for AArch64, thus
avoiding unnecessary calls to tc->readMiscReg(MISCREG_CPSR) in the
non-faulting case.
Diffstat (limited to 'src/arch/arm/utility.hh')
| -rw-r--r-- | src/arch/arm/utility.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index 0c29ac90e..9268a0d5c 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -168,6 +168,8 @@ bool isBigEndian64(ThreadContext *tc); * @param el The controlled exception level. * @return The purified address. */ +Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el, + TTBCR tcr); Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el); static inline bool |