arch-arm: Refactor AArch64 MSR/MRS trapping

This patch refactors AArch64 MSR/MRS trapping, by moving the trapping
helpers in arch/arm/utility and in the isa code into a MiscRegOp64
class.

This class is the Base class for a generic AArch64 instruction which is
making use of system registers (MiscReg), like MSR,MRS,SYS.  The common
denominator or those instruction is the chance that the system register
access is trapped to an upper Exception level. MiscRegOp64 is providing
that feature.

What do we gain? Other "pseudo" instructions, like access to
implementation defined registers can inherit from this class to make use
of the trapping functionalities even if there is no data movement
between GPRs and system register.

Change-Id: I0924354db100de04f1079a1ab43d4fd32039e08d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13778
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 0 insertions, 8 deletions

diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index a31b69588..33696984e 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -310,14 +310,6 @@ bool
 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
                     HCR hcr, uint32_t iss);
 
-bool msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el,
-                       CPACR cpacr);
-bool msrMrs64TrapToHyp(const MiscRegIndex miscReg, ExceptionLevel el,
-                       bool isRead, CPTR cptr, HCR hcr, SCR scr,
-                       CPSR cpsr, bool * isVfpNeon);
-bool msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr,
-                       ExceptionLevel el, bool * isVfpNeon);
-
 bool SPAlignmentCheckEnabled(ThreadContext* tc);
 
 uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);