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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:21:07 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:21:07 -0700 |
| commit | 71e0d1ded278a85e33a628ddc842c975a216854f (patch) | |
| tree | 38b6d745885794a55021ab2f80f565dd4ed89fa8 /src/arch/arm/utility.hh | |
| parent | 19a1966079442ccbcda70c33bbcead7abb609985 (diff) | |
| download | gem5-71e0d1ded278a85e33a628ddc842c975a216854f.tar.xz | |
ARM: Pull some static code out of the isa desc and create miscregs.hh.
Diffstat (limited to 'src/arch/arm/utility.hh')
| -rw-r--r-- | src/arch/arm/utility.hh | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index e0ae7cd2e..a31fcd841 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -33,6 +33,7 @@ #ifndef __ARCH_ARM_UTILITY_HH__ #define __ARCH_ARM_UTILITY_HH__ +#include "arch/arm/miscregs.hh" #include "arch/arm/types.hh" #include "base/misc.hh" #include "base/types.hh" @@ -43,6 +44,32 @@ class ThreadContext; namespace ArmISA { + inline bool + testPredicate(CPSR cpsr, ConditionCode code) + { + switch (code) + { + case COND_EQ: return cpsr.z; + case COND_NE: return !cpsr.z; + case COND_CS: return cpsr.c; + case COND_CC: return !cpsr.c; + case COND_MI: return cpsr.n; + case COND_PL: return !cpsr.n; + case COND_VS: return cpsr.v; + case COND_VC: return !cpsr.v; + case COND_HI: return (cpsr.c && !cpsr.z); + case COND_LS: return !(cpsr.c && !cpsr.z); + case COND_GE: return !(cpsr.n ^ cpsr.v); + case COND_LT: return (cpsr.n ^ cpsr.v); + case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z); + case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z); + case COND_AL: return true; + case COND_NV: return false; + default: + panic("Unhandled predicate condition: %d\n", code); + } + } + //Floating Point Utility Functions uint64_t fpConvert(ConvertType cvt_type, double fp_val); double roundFP(double val, int digits); |