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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-02-19 10:20:14 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-05-23 08:32:25 +0000 |
| commit | 92518ec8437b422f86f7c315a83d9c2aa5fdbe1b (patch) | |
| tree | f2a9e55d8e8c22bb32bc8fa8df81c97903b5391a /src/arch/arm/utility.hh | |
| parent | b8a4c876905d605cf180e77f7d1bb08f2ed22940 (diff) | |
| download | gem5-92518ec8437b422f86f7c315a83d9c2aa5fdbe1b.tar.xz | |
arch-arm: Change mcrMrc15TrapToHyp signature
This patch is moving MiscRegs reading inside the mcrMrc15TrapToHyp
helper function. Rather than passing registers as arguments,
we are just passing a ThreadContext pointer
Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17988
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/utility.hh')
| -rw-r--r-- | src/arch/arm/utility.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index c6ff9469d..15daeb8cf 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -313,8 +313,8 @@ msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, } bool -mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, - HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss); +mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss); + bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss); |