Port: Add protocol-agnostic ports in the port hierarchy

This patch adds an additional level of ports in the inheritance
hierarchy, separating out the protocol-specific and protocl-agnostic
parts. All the functionality related to the binding of ports is now
confined to use BaseMaster/BaseSlavePorts, and all the
protocol-specific parts stay in the Master/SlavePort. In the future it
will be possible to add other protocol-specific implementations.

The functions used in the binding of ports, i.e. getMaster/SlavePort
now use the base classes, and the index parameter is updated to use
the PortID typedef with the symbolic InvalidPortID as the default.

4 files changed, 6 insertions, 6 deletions

diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index dbd4211d5..5f4453935 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -110,8 +110,8 @@ TableWalker::resume()
     }
 }
 
-MasterPort&
-TableWalker::getMasterPort(const std::string &if_name, int idx)
+BaseMasterPort&
+TableWalker::getMasterPort(const std::string &if_name, PortID idx)
 {
     if (if_name == "port") {
         return port;
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 509b24339..22c5d03b4 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -399,8 +399,8 @@ class TableWalker : public MemObject
     void completeDrain();
     virtual unsigned int drain(Event *de);
     virtual void resume();
-    virtual MasterPort& getMasterPort(const std::string &if_name,
-                                      int idx = -1);
+    virtual BaseMasterPort& getMasterPort(const std::string &if_name,
+                                          PortID idx = InvalidPortID);
 
     Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
             TLB::Translation *_trans, bool timing, bool functional = false);
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index f9b2e6fe7..e7ac935e6 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -722,7 +722,7 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
     return fault;
 }
 
-MasterPort*
+BaseMasterPort*
 TLB::getMasterPort()
 {
     return &tableWalker->getMasterPort("port");
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index a20957f6a..968699764 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -224,7 +224,7 @@ class TLB : public BaseTLB
      *
      * @return A pointer to the walker master port
      */
-    virtual MasterPort* getMasterPort();
+    virtual BaseMasterPort* getMasterPort();
 
     // Caching misc register values here.
     // Writing to misc registers needs to invalidate them.