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authorAli Saidi <Ali.Saidi@ARM.com>2009-11-17 18:02:09 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2009-11-17 18:02:09 -0600
commit422f0d9f10c6c3899be5992f9e5555598d4de0d2 (patch)
treef7f1935233dcec259a2b87da2afccf53c146a280 /src/arch/arm
parent0916c376a97dacf5d11589cfea084f0e7feda4cf (diff)
downloadgem5-422f0d9f10c6c3899be5992f9e5555598d4de0d2.tar.xz
ARM: Begin implementing CP15
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/insts/static_inst.cc1
-rw-r--r--src/arch/arm/isa/bitfields.isa1
-rw-r--r--src/arch/arm/isa/decoder.isa51
-rw-r--r--src/arch/arm/types.hh1
-rw-r--r--src/arch/arm/utility.cc16
-rw-r--r--src/arch/arm/utility.hh3
6 files changed, 69 insertions, 4 deletions
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 5181041d0..bf7a38c58 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -27,6 +27,7 @@
* Authors: Stephen Hines
*/
+#include "arch/arm/faults.hh"
#include "arch/arm/insts/static_inst.hh"
#include "base/condcodes.hh"
#include "base/cprintf.hh"
diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa
index bd4cfc320..8ff819983 100644
--- a/src/arch/arm/isa/bitfields.isa
+++ b/src/arch/arm/isa/bitfields.isa
@@ -49,6 +49,7 @@ def bitfield OPCODE_18 opcode18;
def bitfield OPCODE_15_12 opcode15_12;
def bitfield OPCODE_15 opcode15;
def bitfield MISC_OPCODE miscOpcode;
+def bitfield OPC2 opc2;
def bitfield OPCODE_7 opcode7;
def bitfield OPCODE_4 opcode4;
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index 5a6e8773a..ff20c6107 100644
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -493,10 +493,53 @@ format DataOp {
}
} // MEDIA_OPCODE (MISC_OPCODE 0x1)
} // MISC_OPCODE (CPNUM 0xA)
- 0xf: decode OPCODE_20 {
- 0: WarnUnimpl::mcr_cp15();
- 1: WarnUnimpl::mrc_cp15();
- }
+ 0xf: decode RN {
+ // Barrriers, Cache Maintence, NOPS
+ 7: decode OPCODE_23_21 {
+ 0: decode RM {
+ 0: decode OPC2 {
+ 4: decode OPCODE_20 {
+ 0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
+ }
+ }
+ 1: WarnUnimpl::cp15_cache_maint();
+ 4: WarnUnimpl::cp15_par();
+ 5: decode OPC2 {
+ 0,1: WarnUnimpl::cp15_cache_maint2();
+ 4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
+ 6,7: WarnUnimpl::cp15_bp_maint();
+ }
+ 6: WarnUnimpl::cp15_cache_maint3();
+ 8: WarnUnimpl::cp15_va_to_pa();
+ 10: decode OPC2 {
+ 1,2: WarnUnimpl::cp15_cache_maint3();
+ 4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
+ 5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
+ }
+ 11: WarnUnimpl::cp15_cache_maint4();
+ 13: decode OPC2 {
+ 1: decode OPCODE_20 {
+ 0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
+ }
+ }
+ 14: WarnUnimpl::cp15_cache_maint5();
+ } // RM
+ } // OPCODE_23_21 CR
+
+ // Thread ID and context ID registers
+ // Thread ID register needs cheaper access than miscreg
+ 13: WarnUnimpl::mcr_mrc_cp15_c7();
+
+ // All the rest
+ default: decode OPCODE_20 {
+ 0: PredOp::mcr_cp15({{
+ fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
+ }});
+ 1: PredOp::mrc_cp15({{
+ fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
+ }});
+ }
+ } // RN
} // CPNUM (OP4 == 1)
} //OPCODE_4
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 07fa33ea1..e0b3951b9 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -58,6 +58,7 @@ namespace ArmISA
Bitfield<15, 12> opcode15_12;
Bitfield<15> opcode15;
Bitfield<7, 4> miscOpcode;
+ Bitfield<7,5> opc2;
Bitfield<7> opcode7;
Bitfield<4> opcode4;
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index afff97d31..5ce32542b 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -57,4 +57,20 @@ uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
#endif
}
+Fault
+setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2)
+{
+ return new UnimpFault(csprintf("MCR CP15: CRn: %d opc1: %d CRm: %d opc1: %d\n",
+ CRn, opc1, CRm, opc2));
+}
+
+Fault
+readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2)
+{
+ return new UnimpFault(csprintf("MRC CP15: CRn: %d opc1: %d CRm: %d opc1: %d\n",
+ CRn, opc1, CRm, opc2));
+
+}
+
+
}
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 43e7b14ab..3ddfd12dd 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -135,6 +135,9 @@ namespace ArmISA {
}
uint64_t getArgument(ThreadContext *tc, int number, bool fp);
+
+Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
+Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
};