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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:07 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:07 -0500
commit498f9d925e0339389a19bb63d9508e6c780ba04b (patch)
tree00a1726357e965be3a12208c6fcd59e646753bd6 /src/arch/arm
parentf581fd3f899648f8699f53ecdc913e7d50c26f8f (diff)
downloadgem5-498f9d925e0339389a19bb63d9508e6c780ba04b.tar.xz
ARM: Add a base class for the sel instruction.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/insts/misc.cc13
-rw-r--r--src/arch/arm/insts/misc.hh16
-rw-r--r--src/arch/arm/isa/templates/misc.isa24
3 files changed, 53 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index c5430400d..b5ae61f5a 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -169,6 +169,19 @@ RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
}
std::string
+RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ss << ", ";
+ printReg(ss, op1);
+ ss << ", ";
+ printReg(ss, op2);
+ return ss.str();
+}
+
+std::string
RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index d990070fb..8ab0b352a 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -142,6 +142,22 @@ class RegRegRegImmOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+class RegRegRegOp : public PredOp
+{
+ protected:
+ IntRegIndex dest;
+ IntRegIndex op1;
+ IntRegIndex op2;
+
+ RegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
+ PredOp(mnem, _machInst, __opClass),
+ dest(_dest), op1(_op1), op2(_op2)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
class RegImmRegShiftOp : public PredOp
{
protected:
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 3b4c6a6f8..8e781b540 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -146,6 +146,30 @@ def template RegRegRegImmOpConstructor {{
}
}};
+def template RegRegRegOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+ protected:
+ public:
+ // Constructor
+ %(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2);
+ %(BasicExecDeclare)s
+};
+}};
+
+def template RegRegRegOpConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest,
+ IntRegIndex _op1,
+ IntRegIndex _op2)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ _dest, _op1, _op2)
+ {
+ %(constructor)s;
+ }
+}};
+
def template RegImmRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{