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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:07 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:07 -0500
commit554fb3774e638c9a6e7ce4b10a6da6d795a29206 (patch)
tree4d4e5030537888a555d8ed682012db491f413a27 /src/arch/arm
parentcb2e3b0acedbad6b35c0b2a56141399cf4d1c522 (diff)
downloadgem5-554fb3774e638c9a6e7ce4b10a6da6d795a29206.tar.xz
ARM: Add a base class for extend and add instructions.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/insts/misc.cc14
-rw-r--r--src/arch/arm/insts/misc.hh18
-rw-r--r--src/arch/arm/isa/templates/misc.isa26
3 files changed, 58 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index f8106c33a..c5430400d 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -155,6 +155,20 @@ RevOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
}
std::string
+RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ss << ", ";
+ printReg(ss, op1);
+ ss << ", ";
+ printReg(ss, op2);
+ ccprintf(ss, ", #%d", imm);
+ return ss.str();
+}
+
+std::string
RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index fed2e2479..d990070fb 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -124,6 +124,24 @@ class RegImmRegOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+class RegRegRegImmOp : public PredOp
+{
+ protected:
+ IntRegIndex dest;
+ IntRegIndex op1;
+ IntRegIndex op2;
+ uint32_t imm;
+
+ RegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ uint32_t _imm) :
+ PredOp(mnem, _machInst, __opClass),
+ dest(_dest), op1(_op1), op2(_op2), imm(_imm)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
class RegImmRegShiftOp : public PredOp
{
protected:
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index ec660c5a1..3b4c6a6f8 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -120,6 +120,32 @@ def template RevOpConstructor {{
}
}};
+def template RegRegRegImmOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+ protected:
+ public:
+ // Constructor
+ %(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ uint32_t _imm);
+ %(BasicExecDeclare)s
+};
+}};
+
+def template RegRegRegImmOpConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest,
+ IntRegIndex _op1,
+ IntRegIndex _op2,
+ uint32_t _imm)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ _dest, _op1, _op2, _imm)
+ {
+ %(constructor)s;
+ }
+}};
+
def template RegImmRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{