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authorAnouk Van Laer <anouk.vanlaer@arm.com>2018-09-04 11:44:42 +0100
committerAnouk Van Laer <anouk.vanlaer@arm.com>2018-09-13 09:08:19 +0000
commit91295ff980c17efb3ad013b9636017b58e49c071 (patch)
treea9e1d23baf777704579d3c1d348eebb6c88f7d71 /src/arch/arm
parent67f5af9a4da49cd58b35d0f521266051715d9738 (diff)
downloadgem5-91295ff980c17efb3ad013b9636017b58e49c071.tar.xz
arch-arm: Correction for address size in EL1&0 translation
When doing EL0/1 translation in stage2, the physical address size will be defined by the hypervisor (via VTCR_EL2.ps, not TCR.ips). See D10.2.121 of the ARM ARM. Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12552 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/miscregs.hh1
-rw-r--r--src/arch/arm/table_walker.cc49
2 files changed, 27 insertions, 23 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index c1d5efa10..50e64777c 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1810,6 +1810,7 @@ namespace ArmISA
Bitfield<11, 10> orgn0;
Bitfield<13, 12> sh0;
Bitfield<15, 14> tg0;
+ Bitfield<18, 16> ps; // Only defined for VTCR_EL2
EndBitUnion(VTCR_t)
BitUnion32(PRRR)
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 66714fff8..1a7b5d375 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -771,30 +771,33 @@ TableWalker::processWalkAArch64()
start_lookup_level = SLL[sl_tg];
panic_if(start_lookup_level == MAX_LOOKUP_LEVELS,
"Cannot discern lookup level from vtcr.{sl0,tg0}");
- } else switch (bits(currState->vaddr, 63,48)) {
- case 0:
- DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
- ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
- tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
- tg = GrainMap_tg0[currState->tcr.tg0];
- if (bits(currState->vaddr, 63, tsz) != 0x0 ||
- currState->tcr.epd0)
- fault = true;
- break;
- case 0xffff:
- DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
- ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
- tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
- tg = GrainMap_tg1[currState->tcr.tg1];
- if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
- currState->tcr.epd1)
- fault = true;
- break;
- default:
- // top two bytes must be all 0s or all 1s, else invalid addr
- fault = true;
+ ps = currState->vtcr.ps;
+ } else {
+ switch (bits(currState->vaddr, 63,48)) {
+ case 0:
+ DPRINTF(TLB, " - Selecting TTBR0 (AArch64)\n");
+ ttbr = currState->tc->readMiscReg(MISCREG_TTBR0_EL1);
+ tsz = adjustTableSizeAArch64(64 - currState->tcr.t0sz);
+ tg = GrainMap_tg0[currState->tcr.tg0];
+ if (bits(currState->vaddr, 63, tsz) != 0x0 ||
+ currState->tcr.epd0)
+ fault = true;
+ break;
+ case 0xffff:
+ DPRINTF(TLB, " - Selecting TTBR1 (AArch64)\n");
+ ttbr = currState->tc->readMiscReg(MISCREG_TTBR1_EL1);
+ tsz = adjustTableSizeAArch64(64 - currState->tcr.t1sz);
+ tg = GrainMap_tg1[currState->tcr.tg1];
+ if (bits(currState->vaddr, 63, tsz) != mask(64-tsz) ||
+ currState->tcr.epd1)
+ fault = true;
+ break;
+ default:
+ // top two bytes must be all 0s or all 1s, else invalid addr
+ fault = true;
+ }
+ ps = currState->tcr.ips;
}
- ps = currState->tcr.ips;
break;
case EL2:
switch(bits(currState->vaddr, 63,48)) {