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authorGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
committerGene Wu <Gene.Wu@arm.com>2010-08-23 11:18:41 -0500
commitaa601750f8161fcd60b1083067d5bcd5e48a7ccc (patch)
treec1ed9d9f25059cf7d695729f9d758e4810bb5cad /src/arch/arm
parent7405f4b7740a4f90c7f5946a1cfb39163d7b8b1d (diff)
downloadgem5-aa601750f8161fcd60b1083067d5bcd5e48a7ccc.tar.xz
ARM: For non-cachable accesses set the UNCACHABLE flag
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/tlb.cc4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index b7e951767..afa45901a 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -360,6 +360,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
// a bit of a hack but this effectively clrears this processors monitor
if (flags & Clrex){
req->setPaddr(0);
+ req->setFlags(Request::UNCACHEABLE);
return NoFault;
}
if (!is_fetch) {
@@ -430,7 +431,8 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
outerAttrs: %d\n",
te->shareable, te->innerAttrs, te->outerAttrs);
setAttr(te->attributes);
-
+ if (te->nonCacheable)
+ req->setFlags(Request::UNCACHEABLE);
uint32_t dacr = tc->readMiscReg(MISCREG_DACR);
switch ( (dacr >> (te->domain * 2)) & 0x3) {
case 0: