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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:00 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:00 -0500
commitaf91d272711632e63514d5d5866e0f60bf7974d6 (patch)
tree3d4aeaa74255395c50d1b5853d467f6cc05dfac5 /src/arch/arm
parentbfe1a194ddf371a9520023765ade1070d89232d5 (diff)
downloadgem5-af91d272711632e63514d5d5866e0f60bf7974d6.tar.xz
ARM: Add a base class for 32 bit thumb data processing immediate instructions.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/insts/pred_inst.cc17
-rw-r--r--src/arch/arm/insts/pred_inst.hh67
-rw-r--r--src/arch/arm/isa/formats/pred.isa32
3 files changed, 106 insertions, 10 deletions
diff --git a/src/arch/arm/insts/pred_inst.cc b/src/arch/arm/insts/pred_inst.cc
index f98db1c8e..b1b21677c 100644
--- a/src/arch/arm/insts/pred_inst.cc
+++ b/src/arch/arm/insts/pred_inst.cc
@@ -1,4 +1,17 @@
-/* Copyright (c) 2007-2008 The Florida State University
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -40,7 +53,7 @@ PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
}
std::string
-PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+PredImmOpBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printDataInst(ss, true);
diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh
index 76b5a4cff..817ed44f5 100644
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -1,4 +1,17 @@
-/* Copyright (c) 2007-2008 The Florida State University
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -61,27 +74,65 @@ class PredOp : public ArmStaticInst
/**
* Base class for predicated immediate operations.
*/
-class PredImmOp : public PredOp
+class PredImmOpBase : public PredOp
{
protected:
uint32_t imm;
- uint32_t rotate;
uint32_t rotated_imm;
uint32_t rotated_carry;
/// Constructor
+ PredImmOpBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+ PredOp(mnem, _machInst, __opClass),
+ imm(machInst.imm), rotated_imm(0), rotated_carry(0)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+/**
+ * Base class for regular predicated immediate operations.
+ */
+class PredImmOp : public PredImmOpBase
+{
+ protected:
+
+ uint32_t rotate;
+
+ /// Constructor
PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- PredOp(mnem, _machInst, __opClass),
- imm(machInst.imm), rotate(machInst.rotate << 1),
- rotated_imm(0), rotated_carry(0)
+ PredImmOpBase(mnem, _machInst, __opClass),
+ rotate(machInst.rotate << 1)
{
rotated_imm = rotate_imm(imm, rotate);
if (rotate != 0)
- rotated_carry = (rotated_imm >> 31) & 1;
+ rotated_carry = bits(rotated_imm, 31);
}
+};
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+/**
+ * Base class for modified predicated immediate operations.
+ */
+class PredModImmOp : public PredImmOpBase
+{
+ protected:
+
+ uint8_t ctrlImm;
+ uint8_t dataImm;
+
+
+ /// Constructor
+ PredModImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+ PredImmOpBase(mnem, _machInst, __opClass),
+ ctrlImm(bits(machInst.instBits, 26) << 3 |
+ bits(machInst.instBits, 14, 12)),
+ dataImm(bits(machInst.instBits, 7, 0))
+ {
+ rotated_imm = modified_imm(ctrlImm, dataImm);
+ rotated_carry = bits(rotated_imm, 31);
+ }
};
/**
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa
index 0d6ee32f7..03eb3a492 100644
--- a/src/arch/arm/isa/formats/pred.isa
+++ b/src/arch/arm/isa/formats/pred.isa
@@ -1,5 +1,17 @@
// -*- mode:c++ -*-
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder. You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
@@ -165,6 +177,9 @@ let {{
elif flagtype == "rsb":
icValue = 'findCarry(32, resTemp, rotated_imm, ~Rn)'
ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)'
+ elif flagtype == "modImm":
+ icValue = 'rotated_carry'
+ ivValue = 'CondCodes<28:>'
else:
icValue = '(rotate ? rotated_carry:CondCodes<29:>)'
ivValue = 'CondCodes<28:>'
@@ -223,6 +238,23 @@ def format DataImmOp(code, flagtype = logic) {{
decode_block = DataImmDecode.subst(iop)
}};
+def format DataModImmOp(code, flagtype = modImm) {{
+ code += "resTemp = resTemp;"
+ iop = InstObjParams(name, Name + "ModImm", 'PredModImmOp',
+ {"code": code,
+ "predicate_test": predicateTest})
+ ccIop = InstObjParams(name, Name + "ModImmCc", 'PredModImmOp',
+ {"code": code + getImmCcCode(flagtype),
+ "predicate_test": predicateTest})
+ header_output = BasicDeclare.subst(iop) + \
+ BasicDeclare.subst(ccIop)
+ decoder_output = BasicConstructor.subst(iop) + \
+ BasicConstructor.subst(ccIop)
+ exec_output = PredOpExecute.subst(iop) + \
+ PredOpExecute.subst(ccIop)
+ decode_block = DataImmDecode.subst(iop)
+}};
+
def format PredOp(code, *opt_flags) {{
iop = InstObjParams(name, Name, 'PredOp',
{"code": code,