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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 02:01:02 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-08 02:01:02 -0800 |
| commit | d188821d3700ee42e01fc43c9ef17568991fb3ff (patch) | |
| tree | 7aab4499aa0308e60e25a316ee83eec8bb6ae0a9 /src/arch/arm | |
| parent | 3a3e8461511663a3154d0507ba1b0f52ea5366c5 (diff) | |
| download | gem5-d188821d3700ee42e01fc43c9ef17568991fb3ff.tar.xz | |
ARM: Add in more bits for the mon mode.
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa.hh | 3 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 1 | ||||
| -rw-r--r-- | src/arch/arm/types.hh | 1 |
3 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 6341e6cd0..f8359679b 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -63,6 +63,9 @@ namespace ArmISA case MODE_SVC: intRegMap = IntRegSvcMap; break; + case MODE_MON: + intRegMap = IntRegMonMap; + break; case MODE_ABORT: intRegMap = IntRegAbtMap; break; diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 3180669de..ba394d49c 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -59,6 +59,7 @@ namespace ArmISA MISCREG_SPSR_FIQ, MISCREG_SPSR_IRQ, MISCREG_SPSR_SVC, + MISCREG_SPSR_MON, MISCREG_SPSR_UND, MISCREG_SPSR_ABT, MISCREG_FPSR, diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index 2c4e1291c..d5cc07eaf 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -156,6 +156,7 @@ namespace ArmISA MODE_FIQ = 17, MODE_IRQ = 18, MODE_SVC = 19, + MODE_MON = 22, MODE_ABORT = 23, MODE_UNDEFINED = 27, MODE_SYSTEM = 31 |