ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.

3 files changed, 48 insertions, 15 deletions

diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index 6ead79c72..477a1ec60 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -159,20 +159,7 @@ format DataOp {
                         }
                     } // format FloatOp
                 }
-                0xa: decode MISC_OPCODE {
-                    0x1: decode MEDIA_OPCODE {
-                        0xf: decode RN {
-                            0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
-                            0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
-                            0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
-                        }
-                        0xe: decode RN {
-                            0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
-                            0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
-                            0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
-                        }
-                    } // MEDIA_OPCODE (MISC_OPCODE 0x1)
-                } // MISC_OPCODE (CPNUM 0xA)
+                0xa, 0xb: ShortFpTransfer::shortFpTransfer();
                 0xf: McrMrc15::mcrMrc15();
             } // CPNUM  (OP4 == 1)
         } //OPCODE_4
diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa
index 23c33df48..9c64fd37a 100644
--- a/src/arch/arm/isa/decoder/thumb.isa
+++ b/src/arch/arm/isa/decoder/thumb.isa
@@ -86,7 +86,7 @@
                         default: WarnUnimpl::cdp(); // cdp2
                     }
                     0x1: decode LTCOPROC {
-                        0xa, 0xb: WarnUnimpl::Core_to_extension_transfer();
+                        0xa, 0xb: ShortFpTransfer::shortFpTransfer();
                         default: decode CPNUM {
                             15: McrMrc15::mcrMrc15();
                             default: decode HTOPCODE_4 {
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 65ea100d4..303273d6e 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -207,3 +207,49 @@ def format ExtensionRegLoadStore() {{
     }
     '''
 }};
+
+def format ShortFpTransfer() {{
+    decode_block = '''
+    {
+        const uint32_t l = bits(machInst, 20);
+        const uint32_t c = bits(machInst, 8);
+        const uint32_t a = bits(machInst, 23, 21);
+        const uint32_t b = bits(machInst, 6, 5);
+        if ((machInst.thumb == 1 && bits(machInst, 28) == 1) ||
+            (machInst.thumb == 0 && machInst.condCode == 0xf)) {
+            return new Unknown(machInst);
+        }
+        if (l == 0 && c == 0) {
+            if (a == 0) {
+                // A8-648
+                return new WarnUnimplemented("vmov", machInst);
+            } else if (a == 0x7) {
+                // A8-660
+                // B6-29
+                return new WarnUnimplemented("vmsr", machInst);
+            }
+        } else if (l == 0 && c == 1) {
+            if (bits(a, 2) == 0) {
+                // A8-644
+                return new WarnUnimplemented("vmov", machInst);
+            } else if (bits(b, 1) == 0) {
+                // A8-594
+                return new WarnUnimplemented("vdup", machInst);
+            }
+        } else if (l == 1 && c == 0) {
+            if (a == 0) {
+                // A8-648
+                return new WarnUnimplemented("vmov", machInst);
+            } else if (a == 7) {
+                // A8-658
+                // B6-27
+                return new WarnUnimplemented("vmrs", machInst);
+            }
+        } else {
+            // A8-646
+            return new WarnUnimplemented("vmov", machInst);
+        }
+        return new Unknown(machInst);
+    }
+    '''
+}};