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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:06 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:06 -0500 |
| commit | bcf0454864b32dfc196585963d1a554149420acc (patch) | |
| tree | 982efe5ee6fd212a722c1b7a4f7e74bcf84d9330 /src/arch/arm | |
| parent | 87975aa6917768edb54d0fbd3886a48924bba692 (diff) | |
| download | gem5-bcf0454864b32dfc196585963d1a554149420acc.tar.xz | |
ARM: Decode the SADD8 and SADD16 instructions.
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa/formats/data.isa | 54 |
1 files changed, 23 insertions, 31 deletions
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index dc78a5770..28fb50194 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -234,7 +234,7 @@ def format ArmParallelAddSubtract() {{ case 0x1: switch (op2) { case 0x0: - return new WarnUnimplemented("sadd16", machInst); + return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); case 0x1: return new WarnUnimplemented("sasx", machInst); case 0x2: @@ -242,7 +242,7 @@ def format ArmParallelAddSubtract() {{ case 0x3: return new WarnUnimplemented("ssub16", machInst); case 0x4: - return new WarnUnimplemented("sadd8", machInst); + return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); case 0x7: return new WarnUnimplemented("ssub8", machInst); } @@ -542,11 +542,16 @@ def format Thumb32DataProcReg() {{ if (bits(op2, 2) == 0x0) { const uint32_t op1 = bits(machInst, 22, 20); const uint32_t op2 = bits(machInst, 5, 4); + const IntRegIndex rd = + (IntRegIndex)(uint32_t)bits(machInst, 11, 8); + const IntRegIndex rm = + (IntRegIndex)(uint32_t)bits(machInst, 3, 0); switch (op2) { case 0x0: switch (op1) { case 0x1: - return new WarnUnimplemented("sadd16", machInst); + return new Sadd16RegCc(machInst, rd, + rn, rm, 0, LSL); case 0x2: return new WarnUnimplemented("sasx", machInst); case 0x6: @@ -554,39 +559,26 @@ def format Thumb32DataProcReg() {{ case 0x5: return new WarnUnimplemented("ssub16", machInst); case 0x0: - return new WarnUnimplemented("sadd8", machInst); + return new Sadd8RegCc(machInst, rd, + rn, rm, 0, LSL); case 0x4: return new WarnUnimplemented("ssub8", machInst); } break; case 0x1: - { - IntRegIndex rn = - (IntRegIndex)(uint32_t)bits(machInst, 19, 16); - IntRegIndex rd = - (IntRegIndex)(uint32_t)bits(machInst, 11, 8); - IntRegIndex rm = - (IntRegIndex)(uint32_t)bits(machInst, 3, 0); - switch (op1) { - case 0x1: - return new Qadd16Reg(machInst, rd, - rn, rm, 0, LSL); - case 0x2: - return new QasxReg(machInst, rd, - rn, rm, 0, LSL); - case 0x6: - return new QsaxReg(machInst, rd, - rn, rm, 0, LSL); - case 0x5: - return new Qsub16Reg(machInst, rd, - rn, rm, 0, LSL); - case 0x0: - return new Qsub8Reg(machInst, rd, - rn, rm, 0, LSL); - case 0x4: - return new Qsub8Reg(machInst, rd, - rn, rm, 0, LSL); - } + switch (op1) { + case 0x1: + return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); + case 0x2: + return new QasxReg(machInst, rd, rn, rm, 0, LSL); + case 0x6: + return new QsaxReg(machInst, rd, rn, rm, 0, LSL); + case 0x5: + return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); + case 0x0: + return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); + case 0x4: + return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); } break; case 0x2: |