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authorAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:13 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2010-06-02 12:58:13 -0500
commit5e6d28996ae80f2bd3afeadbb3454a9d1958e3a2 (patch)
tree8bf8082c864205dbd4b5f997161c42d1423bd413 /src/arch/arm
parentaec73ba6af62c8da66fb40e015671541708c1723 (diff)
downloadgem5-5e6d28996ae80f2bd3afeadbb3454a9d1958e3a2.tar.xz
ARM: Move PC mode bits around so they can be used for exectrace
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/isa_traits.hh7
-rw-r--r--src/arch/arm/miscregs.hh7
2 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 00c4c2932..4cffe3bec 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -121,6 +121,13 @@ namespace ArmISA
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;
+
+ // These otherwise unused bits of the PC are used to select a mode
+ // like the J and T bits of the CPSR.
+ static const Addr PcJBitShift = 33;
+ static const Addr PcTBitShift = 34;
+ static const Addr PcModeMask = (ULL(1) << PcJBitShift) |
+ (ULL(1) << PcTBitShift);
};
using namespace ArmISA;
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index ad4f91908..e3e2ca2c2 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -201,13 +201,6 @@ namespace ArmISA
// integer register to allow renaming.
static const uint32_t CondCodesMask = 0xF80F0000;
- // These otherwise unused bits of the PC are used to select a mode
- // like the J and T bits of the CPSR.
- static const Addr PcJBitShift = 33;
- static const Addr PcTBitShift = 34;
- static const Addr PcModeMask = (ULL(1) << PcJBitShift) |
- (ULL(1) << PcTBitShift);
-
BitUnion32(SCTLR)
Bitfield<30> te; // Thumb Exception Enable
Bitfield<29> afe; // Access flag enable