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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-10-17 10:20:45 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-10-17 10:20:45 -0500 |
| commit | cf266f05a97b7a0e613fd10cb01f38fec6a4f16c (patch) | |
| tree | 1d6180180b8839bbcbb0bcf32528fda00423e5b2 /src/arch/arm | |
| parent | 60ce2b34fedcb999e249c7b9d277605303b741cf (diff) | |
| download | gem5-cf266f05a97b7a0e613fd10cb01f38fec6a4f16c.tar.xz | |
cpu: Fix O3 uncacheable load that is replayed but misses the TLB
This change fixes an issue in the O3 CPU where an uncachable instruction
is attempted to be executed before it reaches the head of the ROB. It is
determined to be uncacheable, and is replayed, but a PanicFault is attached
to the instruction to make sure that it is properly executed before
committing. If the TLB entry it was using is replaced in the interveaning
time, the TLB returns a delayed translation when the load is replayed at
the head of the ROB, however the LSQ code can't differntiate between the
old fault and the new one. If the translation isn't complete it can't
be faulting, so clear the fault.
Diffstat (limited to 'src/arch/arm')
0 files changed, 0 insertions, 0 deletions