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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:05 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:05 -0500
commit4fb6fcd82d4b3cdb12ffbcd738080e9c4de7bc8a (patch)
tree7a3c43de36f6e4fa21e14b1e37d7e717f65d511a /src/arch/arm
parent30dd62262231b2b2b30aa66a8b28c6ee41afcf9e (diff)
downloadgem5-4fb6fcd82d4b3cdb12ffbcd738080e9c4de7bc8a.tar.xz
ARM: Decode the scalar saturating add/subtract instructions.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/isa/decoder/arm.isa7
-rw-r--r--src/arch/arm/isa/formats/data.isa22
2 files changed, 23 insertions, 6 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index bfb89b22a..050571240 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -116,12 +116,7 @@ format DataOp {
0x3: decode OPCODE {
0x9: ArmBlxReg::armBlxReg();
}
- 0x5: decode OPCODE {
- 0x8: WarnUnimpl::qadd();
- 0x9: WarnUnimpl::qsub();
- 0xa: WarnUnimpl::qdadd();
- 0xb: WarnUnimpl::qdsub();
- }
+ 0x5: ArmSatAddSub::armSatAddSub();
}
0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
}
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 355a41038..f6e093b80 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -341,6 +341,28 @@ def format ArmDataProcImm() {{
'''
}};
+def format ArmSatAddSub() {{
+ decode_block = '''
+ {
+ IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
+ IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ switch (OPCODE) {
+ case 0x8:
+ return new QaddRegCc(machInst, rd, rm, rn, 0, LSL);
+ case 0x9:
+ return new QsubRegCc(machInst, rd, rm, rn, 0, LSL);
+ case 0xa:
+ return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL);
+ case 0xb:
+ return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL);
+ default:
+ return new Unknown(machInst);
+ }
+ }
+ '''
+}};
+
def format Thumb16ShiftAddSubMoveCmp() {{
decode_block = '''
{