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authorGabe Black <gblack@eecs.umich.edu>2011-07-02 22:34:29 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-07-02 22:34:29 -0700
commitaade13769fc6c666bb855e0745e042c82f9941d6 (patch)
treeb95bd2ff43f1bb84b5d2615e12a6f7788a33a12e /src/arch/arm
parentd42e471baac69f3f853592ae001e8c5c61377cae (diff)
downloadgem5-aade13769fc6c666bb855e0745e042c82f9941d6.tar.xz
ISA: Use readBytes/writeBytes for all instruction level memory operations.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/isa/includes.isa1
-rw-r--r--src/arch/arm/isa/templates/mem.isa33
2 files changed, 18 insertions, 16 deletions
diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index b54545e10..bfd6fedd4 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -80,6 +80,7 @@ output exec {{
#include "arch/arm/faults.hh"
#include "arch/arm/isa_traits.hh"
#include "arch/arm/utility.hh"
+#include "arch/generic/memhelpers.hh"
#include "base/condcodes.hh"
#include "sim/pseudo_inst.hh"
#if defined(linux)
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index cb255feda..422d37326 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -87,8 +87,8 @@ def template SwapExecute {{
%(preacc_code)s;
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem,
- EA, memAccessFlags, &memData);
+ fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+ &memData);
}
if (fault == NoFault) {
@@ -123,8 +123,8 @@ def template SwapInitiateAcc {{
%(preacc_code)s;
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, &memData);
+ fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+ &memData);
}
} else {
xc->setPredicate(false);
@@ -147,7 +147,8 @@ def template SwapCompleteAcc {{
if (%(predicate_test)s)
{
// ARM instructions will not have a pkt if the predicate is false
- uint64_t memData = pkt->get<typeof(Mem)>();
+ getMem(pkt, Mem, traceData);
+ uint64_t memData = Mem;
%(postacc_code)s;
@@ -174,7 +175,7 @@ def template LoadExecute {{
if (%(predicate_test)s)
{
if (fault == NoFault) {
- fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+ fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
%(memacc_code)s;
}
@@ -241,8 +242,8 @@ def template StoreExecute {{
}
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
+ fault = writeMemAtomic(xc, traceData, Mem, EA,
+ memAccessFlags, NULL);
}
if (fault == NoFault) {
@@ -314,8 +315,8 @@ def template StoreExExecute {{
uint64_t writeResult;
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, &writeResult);
+ fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+ &writeResult);
}
if (fault == NoFault) {
@@ -351,8 +352,8 @@ def template StoreExInitiateAcc {{
}
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
+ fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+ NULL);
}
} else {
xc->setPredicate(false);
@@ -380,8 +381,8 @@ def template StoreInitiateAcc {{
}
if (fault == NoFault) {
- fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
+ fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+ NULL);
}
} else {
xc->setPredicate(false);
@@ -437,7 +438,7 @@ def template LoadInitiateAcc {{
if (%(predicate_test)s)
{
if (fault == NoFault) {
- fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
+ fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
}
} else {
xc->setPredicate(false);
@@ -489,7 +490,7 @@ def template LoadCompleteAcc {{
if (%(predicate_test)s)
{
// ARM instructions will not have a pkt if the predicate is false
- Mem = pkt->get<typeof(Mem)>();
+ getMem(pkt, Mem, traceData);
if (fault == NoFault) {
%(memacc_code)s;