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| author | Nathan Binkert <nate@binkert.org> | 2011-06-02 17:36:21 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2011-06-02 17:36:21 -0700 |
| commit | 2b1aa35e209a76515763e7e7d7a0fe6a8267bebf (patch) | |
| tree | fde43c1f169789aa6f10fc58bb70678d1230e756 /src/arch/arm | |
| parent | f49f384fe415e68096d16e0ef5396136bc97b292 (diff) | |
| download | gem5-2b1aa35e209a76515763e7e7d7a0fe6a8267bebf.tar.xz | |
scons: rename TraceFlags to DebugFlags
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/SConscript | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 51aff52f3..a907e52fb 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -65,10 +65,10 @@ if env['TARGET_ISA'] == 'arm': SimObject('ArmNativeTrace.py') SimObject('ArmTLB.py') - TraceFlag('Arm') - TraceFlag('TLBVerbose') - TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi") - TraceFlag('Predecoder', "Instructions returned by the predecoder") + DebugFlag('Arm') + DebugFlag('TLBVerbose') + DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") + DebugFlag('Predecoder', "Instructions returned by the predecoder") if env['FULL_SYSTEM']: Source('interrupts.cc') Source('stacktrace.cc') |