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| author | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
|---|---|---|
| committer | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
| commit | 7405f4b7740a4f90c7f5946a1cfb39163d7b8b1d (patch) | |
| tree | 67c92ce16f244361110389d02202fd5ae0afa6be /src/arch/arm | |
| parent | aabf478920671b8daf5c38a50442e80310e50671 (diff) | |
| download | gem5-7405f4b7740a4f90c7f5946a1cfb39163d7b8b1d.tar.xz | |
ARM: Implement DSB, DMB, ISB
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa/formats/branch.isa | 6 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/uncond.isa | 6 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 27 |
3 files changed, 33 insertions, 6 deletions
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa index 44a2f5251..b1818adf0 100644 --- a/src/arch/arm/isa/formats/branch.isa +++ b/src/arch/arm/isa/formats/branch.isa @@ -196,11 +196,11 @@ def format Thumb32BranchesAndMiscCtrl() {{ case 0x2: return new Clrex(machInst); case 0x4: - return new WarnUnimplemented("dsb", machInst); + return new Dsb(machInst); case 0x5: - return new WarnUnimplemented("dmb", machInst); + return new Dmb(machInst); case 0x6: - return new WarnUnimplemented("isb", machInst); + return new Isb(machInst); default: break; } diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa index 92e4db22d..0ef113607 100644 --- a/src/arch/arm/isa/formats/uncond.isa +++ b/src/arch/arm/isa/formats/uncond.isa @@ -99,11 +99,11 @@ def format ArmUnconditional() {{ case 0x1: return new Clrex(machInst); case 0x4: - return new WarnUnimplemented("dsb", machInst); + return new Dsb(machInst); case 0x5: - return new WarnUnimplemented("dmb", machInst); + return new Dmb(machInst); case 0x6: - return new WarnUnimplemented("isb", machInst); + return new Isb(machInst); } } } else if (bits(op2, 0) == 0) { diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 09364cd23..5a28a9dba 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -679,6 +679,33 @@ let {{ decoder_output += BasicConstructor.subst(clrexIop) exec_output += PredOpExecute.subst(clrexIop) + isbCode = ''' + ''' + isbIop = InstObjParams("isb", "Isb", "PredOp", + {"code": isbCode, + "predicate_test": predicateTest}, ['IsSerializing']) + header_output += BasicDeclare.subst(isbIop) + decoder_output += BasicConstructor.subst(isbIop) + exec_output += PredOpExecute.subst(isbIop) + + dsbCode = ''' + ''' + dsbIop = InstObjParams("dsb", "Dsb", "PredOp", + {"code": dsbCode, + "predicate_test": predicateTest},['IsMemBarrier']) + header_output += BasicDeclare.subst(dsbIop) + decoder_output += BasicConstructor.subst(dsbIop) + exec_output += PredOpExecute.subst(dsbIop) + + dmbCode = ''' + ''' + dmbIop = InstObjParams("dmb", "Dmb", "PredOp", + {"code": dmbCode, + "predicate_test": predicateTest},['IsMemBarrier']) + header_output += BasicDeclare.subst(dmbIop) + decoder_output += BasicConstructor.subst(dmbIop) + exec_output += PredOpExecute.subst(dmbIop) + cpsCode = ''' uint32_t mode = bits(imm, 4, 0); uint32_t f = bits(imm, 5); |