diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:37:41 -0700 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:37:41 -0700 |
commit | c20ce20e4c218e801db6f3495cb6bd1f5870156b (patch) | |
tree | 73df979f0fb24cc9e74c8643996b453188b0154e /src/arch/arm | |
parent | 71e0d1ded278a85e33a628ddc842c975a216854f (diff) | |
download | gem5-c20ce20e4c218e801db6f3495cb6bd1f5870156b.tar.xz |
ARM: Make the isa parser aware that CPSR is being used.
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/isa/decoder.isa | 3 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/branch.isa | 4 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/fp.isa | 31 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/macromem.isa | 10 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/mem.isa | 24 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/pred.isa | 39 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/util.isa | 14 |
7 files changed, 80 insertions, 45 deletions
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa index b84109546..8b4175f9c 100644 --- a/src/arch/arm/isa/decoder.isa +++ b/src/arch/arm/isa/decoder.isa @@ -830,8 +830,7 @@ decode COND_CODE default Unknown::unknown() { } format PredOp { // ARM System Call (SoftWare Interrupt) - 1: swi({{ if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), - condCode)) + 1: swi({{ if (testPredicate(Cpsr, condCode)) { //xc->syscall(R7); xc->syscall(IMMED_23_0); diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa index 15965d3e0..3e69c9532 100644 --- a/src/arch/arm/isa/formats/branch.isa +++ b/src/arch/arm/isa/formats/branch.isa @@ -234,7 +234,7 @@ def format Branch(code,*opt_flags) {{ else: inst_flags += ('IsCondControl', ) - icode = 'if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) {\n' + icode = 'if (testPredicate(Cpsr, condCode)) {\n' icode += code icode += ' NPC = NPC + 4 + disp;\n' icode += '} else {\n' @@ -268,7 +268,7 @@ def format BranchExchange(code,*opt_flags) {{ #Condition code - icode = 'if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) {\n' + icode = 'if (testPredicate(Cpsr, condCode)) {\n' icode += code icode += ' NPC = Rm & 0xfffffffe; // Masks off bottom bit\n' icode += '} else {\n' diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index 1dd05c223..fda1175b0 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -65,12 +65,11 @@ def template FPAExecute {{ %(op_decl)s; %(op_rd)s; - %(code)s; - - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode) && - fault == NoFault) - { - %(op_wb)s; + if (%(predicate_test)s) { + %(code)s; + if (fault == NoFault) { + %(op_wb)s; + } } return fault; @@ -102,13 +101,19 @@ def format FloatOp(code, *flags) {{ orig_code = code cblk = code - iop = InstObjParams(name, Name, 'FPAOp', cblk, flags) + iop = InstObjParams(name, Name, 'FPAOp', + {"code": cblk, + "predicate_test": predicateTest}, + flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) exec_output = FPAExecute.subst(iop) sng_cblk = code - sng_iop = InstObjParams(name, Name+'S', 'FPAOp', sng_cblk, flags) + sng_iop = InstObjParams(name, Name+'S', 'FPAOp', + {"code": sng_cblk, + "predicate_test": predicateTest}, + flags) header_output += BasicDeclare.subst(sng_iop) decoder_output += BasicConstructor.subst(sng_iop) exec_output += FPAExecute.subst(sng_iop) @@ -116,7 +121,10 @@ def format FloatOp(code, *flags) {{ dbl_code = re.sub(r'\.sf', '.df', orig_code) dbl_cblk = dbl_code - dbl_iop = InstObjParams(name, Name+'D', 'FPAOp', dbl_cblk, flags) + dbl_iop = InstObjParams(name, Name+'D', 'FPAOp', + {"code": dbl_cblk, + "predicate_test": predicateTest}, + flags) header_output += BasicDeclare.subst(dbl_iop) decoder_output += BasicConstructor.subst(dbl_iop) exec_output += FPAExecute.subst(dbl_iop) @@ -140,7 +148,10 @@ let {{ def format FloatCmp(fReg1, fReg2, *flags) {{ code = calcFPCcCode % vars() - iop = InstObjParams(name, Name, 'FPAOp', code, flags) + iop = InstObjParams(name, Name, 'FPAOp', + {"code": code, + "predicate_test": predicateTest}, + flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa index bc055d74e..36a43de5e 100644 --- a/src/arch/arm/isa/formats/macromem.isa +++ b/src/arch/arm/isa/formats/macromem.isa @@ -370,7 +370,10 @@ def format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{ }}; def format ArmMacroFPAOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ - iop = InstObjParams(name, Name, 'ArmMacroFPAOp', code, opt_flags) + iop = InstObjParams(name, Name, 'ArmMacroFPAOp', + {"code": code, + "predicate_test": predicateTest}, + opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = MacroFPAConstructor.subst(iop) decode_block = BasicDecode.subst(iop) @@ -378,7 +381,10 @@ def format ArmMacroFPAOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ }}; def format ArmMacroFMOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{ - iop = InstObjParams(name, Name, 'ArmMacroFMOp', code, opt_flags) + iop = InstObjParams(name, Name, 'ArmMacroFMOp', + {"code": code, + "predicate_test": predicateTest}, + opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = MacroFMConstructor.subst(iop) decode_block = BasicDecode.subst(iop) diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa index 4da37c3e7..c5453ec48 100644 --- a/src/arch/arm/isa/formats/mem.isa +++ b/src/arch/arm/isa/formats/mem.isa @@ -216,7 +216,7 @@ def template EACompExecute {{ %(op_rd)s; %(ea_code)s; - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { if (fault == NoFault) { %(op_wb)s; @@ -241,7 +241,7 @@ def template LoadMemAccExecute {{ %(op_rd)s; EA = xc->getEA(); - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { if (fault == NoFault) { fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); @@ -270,7 +270,7 @@ def template LoadExecute {{ %(op_rd)s; %(ea_code)s; - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { if (fault == NoFault) { fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); @@ -299,7 +299,7 @@ def template LoadInitiateAcc {{ %(op_rd)s; %(ea_code)s; - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { if (fault == NoFault) { fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); @@ -322,7 +322,7 @@ def template LoadCompleteAcc {{ %(op_decl)s; %(op_rd)s; - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { // ARM instructions will not have a pkt if the predicate is false Mem = pkt->get<typeof(Mem)>(); @@ -353,7 +353,7 @@ def template StoreMemAccExecute {{ %(op_decl)s; %(op_rd)s; - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { EA = xc->getEA(); @@ -385,7 +385,7 @@ def template StoreExecute {{ %(op_rd)s; %(ea_code)s; - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { if (fault == NoFault) { %(memacc_code)s; @@ -418,7 +418,7 @@ def template StoreInitiateAcc {{ %(op_rd)s; %(ea_code)s; - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { if (fault == NoFault) { %(memacc_code)s; @@ -451,7 +451,7 @@ def template StoreCompleteAcc {{ %(fp_enable_check)s; %(op_dest_decl)s; - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { if (fault == NoFault) { %(op_wb)s; @@ -472,7 +472,7 @@ def template StoreCondCompleteAcc {{ %(fp_enable_check)s; %(op_dest_decl)s; - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { if (fault == NoFault) { %(op_wb)s; @@ -495,7 +495,7 @@ def template MiscMemAccExecute {{ %(op_decl)s; %(op_rd)s; - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { EA = xc->getEA(); @@ -520,7 +520,7 @@ def template MiscExecute {{ %(op_rd)s; %(ea_code)s; - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { if (fault == NoFault) { %(memacc_code)s; diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa index de9f4d316..751c21816 100644 --- a/src/arch/arm/isa/formats/pred.isa +++ b/src/arch/arm/isa/formats/pred.isa @@ -161,26 +161,26 @@ output header {{ }}; +let {{ + predicateTest = 'testPredicate(Cpsr, condCode)' +}}; + def template PredOpExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; - - %(fp_enable_check)s; %(op_decl)s; %(op_rd)s; - %(code)s; - if (testPredicate(xc->readMiscReg(ArmISA::MISCREG_CPSR), condCode)) + if (%(predicate_test)s) { + %(fp_enable_check)s; + %(code)s; if (fault == NoFault) { %(op_wb)s; } } - else - return NoFault; - // Predicated false instructions should not return faults return fault; } @@ -281,7 +281,10 @@ let {{ }}; def format PredOp(code, *opt_flags) {{ - iop = InstObjParams(name, Name, 'PredOp', code, opt_flags) + iop = InstObjParams(name, Name, 'PredOp', + {"code": code, + "predicate_test": predicateTest}, + opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) @@ -289,7 +292,10 @@ def format PredOp(code, *opt_flags) {{ }}; def format PredImmOp(code, *opt_flags) {{ - iop = InstObjParams(name, Name, 'PredImmOp', code, opt_flags) + iop = InstObjParams(name, Name, 'PredImmOp', + {"code": code, + "predicate_test": predicateTest}, + opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) @@ -300,7 +306,10 @@ def format PredImmOpCc(code, icValue, ivValue, *opt_flags) {{ ccCode = calcCcCode % vars() code += ccCode; iop = InstObjParams(name, Name, 'PredImmOp', - {"code": code, "cc_code": ccCode}, opt_flags) + {"code": code, + "cc_code": ccCode, + "predicate_test": predicateTest}, + opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) @@ -309,7 +318,10 @@ def format PredImmOpCc(code, icValue, ivValue, *opt_flags) {{ def format PredIntOp(code, *opt_flags) {{ new_code = ArmGenericCodeSubs(code) - iop = InstObjParams(name, Name, 'PredIntOp', new_code, opt_flags) + iop = InstObjParams(name, Name, 'PredIntOp', + {"code": new_code, + "predicate_test": predicateTest}, + opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) @@ -321,7 +333,10 @@ def format PredIntOpCc(code, icValue, ivValue, *opt_flags) {{ code += ccCode; new_code = ArmGenericCodeSubs(code) iop = InstObjParams(name, Name, 'PredIntOp', - {"code": new_code, "cc_code": ccCode }, opt_flags) + {"code": new_code, + "cc_code": ccCode, + "predicate_test": predicateTest}, + opt_flags) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) diff --git a/src/arch/arm/isa/formats/util.isa b/src/arch/arm/isa/formats/util.isa index 354f936d7..f60988bbb 100644 --- a/src/arch/arm/isa/formats/util.isa +++ b/src/arch/arm/isa/formats/util.isa @@ -58,14 +58,18 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, # they differ only in the set of code objects contained (which in # turn affects the object's overall operand list). iop = InstObjParams(name, Name, base_class, - { 'ea_code':ea_code, 'memacc_code':memacc_code}, + {'ea_code': ea_code, + 'memacc_code': memacc_code, + 'predicate_test': predicateTest}, inst_flags) ea_iop = InstObjParams(name, Name, base_class, - { 'ea_code':ea_code }, - inst_flags) + {'ea_code': ea_code, + 'predicate_test': predicateTest}, + inst_flags) memacc_iop = InstObjParams(name, Name, base_class, - { 'memacc_code':memacc_code}, - inst_flags) + {'memacc_code': memacc_code, + 'predicate_test': predicateTest}, + inst_flags) if mem_flags: s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' |