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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:06 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:06 -0500
commitf19b605aedddcfab1ee2abba87dfeaafe7c8c3c7 (patch)
tree6bbd57f473ff6be254f32480e718675f5bafaf04 /src/arch/arm
parent15356af288c3e32ef9057e7a59e3bba6a2156b43 (diff)
downloadgem5-f19b605aedddcfab1ee2abba87dfeaafe7c8c3c7.tar.xz
ARM: Decode the 16 bit thumb versions of the REV* instructions.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/isa/formats/data.isa22
1 files changed, 13 insertions, 9 deletions
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index b1baca16b..217f1364b 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -649,15 +649,19 @@ def format Thumb16Misc() {{
(bits(machInst, 7, 3) << 1),
(IntRegIndex)(uint32_t)bits(machInst, 2, 0));
case 0xa:
- switch (bits(machInst, 7, 5)) {
- case 0x0:
- return new WarnUnimplemented("rev", machInst);
- case 0x1:
- return new WarnUnimplemented("rev16", machInst);
- case 0x3:
- return new WarnUnimplemented("revsh", machInst);
- default:
- break;
+ {
+ IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
+ IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
+ switch (bits(machInst, 7, 6)) {
+ case 0x0:
+ return new Rev(machInst, rd, rm);
+ case 0x1:
+ return new Rev16(machInst, rd, rm);
+ case 0x3:
+ return new Revsh(machInst, rd, rm);
+ default:
+ break;
+ }
}
break;
case 0xb: