diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:38 -0600 |
commit | 8aaa39e93dfe000ad423b585e78a4c2ee7418363 (patch) | |
tree | 0f7b6d1efb630745bd6bf6af05a722a08c8640cb /src/arch/arm | |
parent | 7e104a1af235823e3d641a972ea920937f7ec67d (diff) | |
download | gem5-8aaa39e93dfe000ad423b585e78a4c2ee7418363.tar.xz |
mem: Add a master ID to each request object.
This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/isa.cc | 3 | ||||
-rw-r--r-- | src/arch/arm/table_walker.cc | 6 | ||||
-rw-r--r-- | src/arch/arm/table_walker.hh | 3 |
3 files changed, 8 insertions, 4 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 5c2478946..a609b3ef9 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -559,7 +559,8 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) panic("Security Extensions not implemented!"); } warn("Translating via MISCREG in atomic mode! Fix Me!\n"); - req->setVirt(0, val, 1, flags, tc->pcState().pc()); + req->setVirt(0, val, 1, flags, tc->pcState().pc(), + Request::funcMasterId); fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); if (fault == NoFault) { miscRegs[MISCREG_PAR] = diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 9c92ebdf6..de3c38e78 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -52,6 +52,7 @@ using namespace ArmISA; TableWalker::TableWalker(const Params *p) : MemObject(p), port(NULL), tlb(NULL), currState(NULL), pending(false), + masterId(p->sys->getMasterId(name())), doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this) { sctlr = 0; @@ -62,7 +63,6 @@ TableWalker::~TableWalker() ; } - unsigned int TableWalker::drain(Event *de) { @@ -239,7 +239,7 @@ TableWalker::processWalk() doL1Descriptor(); f = currState->fault; } else { - RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag); + RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, masterId); PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); pkt->dataStatic((uint8_t*)&currState->l1Desc.data); port->sendFunctional(pkt); @@ -583,7 +583,7 @@ TableWalker::doL1Descriptor() currState->tc->getCpuPtr()->ticks(1)); doL2Descriptor(); } else { - RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0); + RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0, masterId); PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast); pkt->dataStatic((uint8_t*)&currState->l2Desc.data); port->sendFunctional(pkt); diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index d4a2e87b5..520bfd9ac 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -341,6 +341,9 @@ class TableWalker : public MemObject /** If a timing translation is currently in progress */ bool pending; + /** Request id for requests generated by this walker */ + MasterID masterId; + public: typedef ArmTableWalkerParams Params; TableWalker(const Params *p); |