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| author | Ali Saidi <saidi@eecs.umich.edu> | 2010-06-03 12:20:49 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2010-06-03 12:20:49 -0400 |
| commit | d2186857b15ccdfe58b6d9e1369946253c28fb02 (patch) | |
| tree | 8a9bd03b16430c6a99acbcbcb06c2b18a3222946 /src/arch/arm | |
| parent | 5268067f14d1c0b0df81a6aa688009671926d907 (diff) | |
| download | gem5-d2186857b15ccdfe58b6d9e1369946253c28fb02.tar.xz | |
ARM: Fix issue with m5.fast and ARM
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 60f00e438..17f95e57d 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -424,10 +424,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) flags = TLB::MustBeOne | TLB::UserMode; mode = BaseTLB::Write; break; - case MISCREG_V2POWPR: - case MISCREG_V2POWPW: - case MISCREG_V2POWUR: - case MISCREG_V2POWUW: + default: panic("Security Extensions not implemented!"); } req->setVirt(0, val, 1, flags, tc->readPC()); |