summaryrefslogtreecommitdiff
path: root/src/arch/arm
diff options
context:
space:
mode:
authorNathan Binkert <nate@binkert.org>2011-06-02 17:36:21 -0700
committerNathan Binkert <nate@binkert.org>2011-06-02 17:36:21 -0700
commit2b1aa35e209a76515763e7e7d7a0fe6a8267bebf (patch)
treefde43c1f169789aa6f10fc58bb70678d1230e756 /src/arch/arm
parentf49f384fe415e68096d16e0ef5396136bc97b292 (diff)
downloadgem5-2b1aa35e209a76515763e7e7d7a0fe6a8267bebf.tar.xz
scons: rename TraceFlags to DebugFlags
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/SConscript8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 51aff52f3..a907e52fb 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -65,10 +65,10 @@ if env['TARGET_ISA'] == 'arm':
SimObject('ArmNativeTrace.py')
SimObject('ArmTLB.py')
- TraceFlag('Arm')
- TraceFlag('TLBVerbose')
- TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
- TraceFlag('Predecoder', "Instructions returned by the predecoder")
+ DebugFlag('Arm')
+ DebugFlag('TLBVerbose')
+ DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
+ DebugFlag('Predecoder', "Instructions returned by the predecoder")
if env['FULL_SYSTEM']:
Source('interrupts.cc')
Source('stacktrace.cc')