diff options
author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
---|---|---|
committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/arch/arm | |
parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/insts/static_inst.cc | 2 | ||||
-rw-r--r-- | src/arch/arm/isa.hh | 7 | ||||
-rw-r--r-- | src/arch/arm/registers.hh | 7 | ||||
-rw-r--r-- | src/arch/arm/utility.cc | 11 |
4 files changed, 22 insertions, 5 deletions
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc index 3ab7dfb0e..2a8dee162 100644 --- a/src/arch/arm/insts/static_inst.cc +++ b/src/arch/arm/insts/static_inst.cc @@ -239,6 +239,8 @@ ArmStaticInst::printReg(std::ostream &os, int reg) const assert(rel_reg < NUM_MISCREGS); ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]); break; + case CCRegClass: + panic("printReg: CCRegClass but ARM has no CC regs\n"); } } diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index e7abb26b2..6fd57549a 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -140,6 +140,13 @@ namespace ArmISA return reg; } + // dummy + int + flattenCCIndex(int reg) + { + return reg; + } + int flattenMiscIndex(int reg) { diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index cc4fac824..b9033fd5b 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -68,6 +68,9 @@ typedef float FloatReg; // cop-0/cop-1 system control register typedef uint64_t MiscReg; +// dummy typedef since we don't have CC regs +typedef uint8_t CCReg; + // Constants Related to the number of registers const int NumIntArchRegs = NUM_ARCH_INTREGS; // The number of single precision floating point registers @@ -76,6 +79,7 @@ const int NumFloatSpecialRegs = 8; const int NumIntRegs = NUM_INTREGS; const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; +const int NumCCRegs = 0; const int NumMiscRegs = NUM_MISCREGS; const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; @@ -102,7 +106,8 @@ const int SyscallSuccessReg = ReturnValueReg; // These help enumerate all the registers for dependence tracking. const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1); -const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs; +const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; +const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; typedef union { diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 776c1ae82..cddc2c5c4 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -113,7 +113,7 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) void skipFunction(ThreadContext *tc) { - TheISA::PCState newPC = tc->pcState(); + PCState newPC = tc->pcState(); newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1)); CheckerCPU *checker = tc->getCheckerCpuPtr(); @@ -127,13 +127,16 @@ skipFunction(ThreadContext *tc) void copyRegs(ThreadContext *src, ThreadContext *dest) { - for (int i = 0; i < TheISA::NumIntRegs; i++) + for (int i = 0; i < NumIntRegs; i++) dest->setIntRegFlat(i, src->readIntRegFlat(i)); - for (int i = 0; i < TheISA::NumFloatRegs; i++) + for (int i = 0; i < NumFloatRegs; i++) dest->setFloatRegFlat(i, src->readFloatRegFlat(i)); - for (int i = 0; i < TheISA::NumMiscRegs; i++) + // Would need to add condition-code regs if implemented + assert(NumCCRegs == 0); + + for (int i = 0; i < NumMiscRegs; i++) dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); // setMiscReg "with effect" will set the misc register mapping correctly. |