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authorAli Saidi <Ali.Saidi@ARM.com>2012-03-21 10:34:06 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2012-03-21 10:34:06 -0500
commited8ed6e7614057e0c8f7461ea9f7a8f2d59a57ea (patch)
tree8060e538952556840abf34a9e0fac574eb093194 /src/arch/arm
parenta64319f764cfa8c961696c4fab996a50b45ab09e (diff)
downloadgem5-ed8ed6e7614057e0c8f7461ea9f7a8f2d59a57ea.tar.xz
ARM: Clean up condCodes in IT blocks.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/insts/branch.hh26
-rw-r--r--src/arch/arm/isa/formats/branch.isa25
-rw-r--r--src/arch/arm/isa/formats/data.isa16
3 files changed, 17 insertions, 50 deletions
diff --git a/src/arch/arm/insts/branch.hh b/src/arch/arm/insts/branch.hh
index 0e33a9214..cc320dbff 100644
--- a/src/arch/arm/insts/branch.hh
+++ b/src/arch/arm/insts/branch.hh
@@ -63,16 +63,15 @@ class BranchImm : public PredOp
// Conditionally Branch to a target computed with an immediate
class BranchImmCond : public BranchImm
{
- protected:
- // This will mask the condition code stored for PredOp. Ideally these two
- // class would cooperate, but they're not set up to do that at the moment.
- ConditionCode condCode;
-
public:
BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
int32_t _imm, ConditionCode _condCode) :
- BranchImm(mnem, _machInst, __opClass, _imm), condCode(_condCode)
- {}
+ BranchImm(mnem, _machInst, __opClass, _imm)
+ {
+ // Only update if this isn't part of an IT block
+ if (!machInst.itstateMask)
+ condCode = _condCode;
+ }
};
// Branch to a target computed with a register
@@ -91,16 +90,15 @@ class BranchReg : public PredOp
// Conditionally Branch to a target computed with a register
class BranchRegCond : public BranchReg
{
- protected:
- // This will mask the condition code stored for PredOp. Ideally these two
- // class would cooperate, but they're not set up to do that at the moment.
- ConditionCode condCode;
-
public:
BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _op1, ConditionCode _condCode) :
- BranchReg(mnem, _machInst, __opClass, _op1), condCode(_condCode)
- {}
+ BranchReg(mnem, _machInst, __opClass, _op1)
+ {
+ // Only update if this isn't part of an IT block
+ if (!machInst.itstateMask)
+ condCode = _condCode;
+ }
};
// Branch to a target computed with two registers
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index fccfe2897..f1b17ec90 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -236,13 +236,6 @@ def format Thumb32BranchesAndMiscCtrl() {{
}
case 0x1:
{
- ConditionCode condCode;
- if(machInst.itstateMask) {
- condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
- } else {
- condCode = COND_UC;
- }
-
const uint32_t s = bits(machInst, 26);
const uint32_t i1 = !(bits(machInst, 13) ^ s);
const uint32_t i2 = !(bits(machInst, 11) ^ s);
@@ -251,19 +244,13 @@ def format Thumb32BranchesAndMiscCtrl() {{
const int32_t imm = sext<25>((s << 24) |
(i1 << 23) | (i2 << 22) |
(imm10 << 12) | (imm11 << 1));
- return new B(machInst, imm, condCode);
+ return new B(machInst, imm, COND_UC);
}
case 0x4:
{
if (bits(machInst, 0) == 1) {
return new Unknown(machInst);
}
- ConditionCode condCode;
- if(machInst.itstateMask) {
- condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
- } else {
- condCode = COND_UC;
- }
const uint32_t s = bits(machInst, 26);
const uint32_t i1 = !(bits(machInst, 13) ^ s);
const uint32_t i2 = !(bits(machInst, 11) ^ s);
@@ -272,16 +259,10 @@ def format Thumb32BranchesAndMiscCtrl() {{
const int32_t imm = sext<25>((s << 24) |
(i1 << 23) | (i2 << 22) |
(imm10h << 12) | (imm10l << 2));
- return new BlxImm(machInst, imm, condCode);
+ return new BlxImm(machInst, imm, COND_UC);
}
case 0x5:
{
- ConditionCode condCode;
- if(machInst.itstateMask) {
- condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
- } else {
- condCode = COND_UC;
- }
const uint32_t s = bits(machInst, 26);
const uint32_t i1 = !(bits(machInst, 13) ^ s);
const uint32_t i2 = !(bits(machInst, 11) ^ s);
@@ -290,7 +271,7 @@ def format Thumb32BranchesAndMiscCtrl() {{
const int32_t imm = sext<25>((s << 24) |
(i1 << 23) | (i2 << 22) |
(imm10 << 12) | (imm11 << 1));
- return new Bl(machInst, imm, condCode);
+ return new Bl(machInst, imm, COND_UC);
}
default:
break;
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index ffe5f45e3..3ee178f0e 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -1040,25 +1040,13 @@ def format Thumb16SpecDataAndBx() {{
return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
case 0x3:
if (bits(machInst, 7) == 0) {
- ConditionCode condCode;
- if(machInst.itstateMask) {
- condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
- } else {
- condCode = COND_UC;
- }
return new BxReg(machInst,
(IntRegIndex)(uint32_t)bits(machInst, 6, 3),
- condCode);
+ COND_UC);
} else {
- ConditionCode condCode;
- if(machInst.itstateMask) {
- condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
- } else {
- condCode = COND_UC;
- }
return new BlxReg(machInst,
(IntRegIndex)(uint32_t)bits(machInst, 6, 3),
- condCode);
+ COND_UC);
}
}
}