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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:08 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:08 -0500
commitb1158e493843066acdba153c89573273f5d0fd73 (patch)
tree1ec9ac7d5355ec1ed6a3335cad8996449fb39e82 /src/arch/arm
parent504ac6518bea90d614c2d2394fa3881f8557d798 (diff)
downloadgem5-b1158e493843066acdba153c89573273f5d0fd73.tar.xz
ARM: Add a register, immediate, immediate to register base for [su]bfx.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/insts/misc.cc12
-rw-r--r--src/arch/arm/insts/misc.hh18
-rw-r--r--src/arch/arm/isa/templates/misc.isa26
3 files changed, 56 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 3ad49bb9d..20f102e72 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -197,6 +197,18 @@ RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
}
std::string
+RegRegImmImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ printMnemonic(ss);
+ printReg(ss, dest);
+ ss << ", ";
+ printReg(ss, op1);
+ ccprintf(ss, ", #%d, #%d", imm1, imm2);
+ return ss.str();
+}
+
+std::string
RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 7ee2d95f9..b5a75d20d 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -176,6 +176,24 @@ class RegRegRegOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+class RegRegImmImmOp : public PredOp
+{
+ protected:
+ IntRegIndex dest;
+ IntRegIndex op1;
+ uint32_t imm1;
+ uint32_t imm2;
+
+ RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+ IntRegIndex _dest, IntRegIndex _op1,
+ uint32_t _imm1, uint32_t _imm2) :
+ PredOp(mnem, _machInst, __opClass),
+ dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
class RegImmRegShiftOp : public PredOp
{
protected:
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 7a9a35ec9..83d165365 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -196,6 +196,32 @@ def template RegRegRegOpConstructor {{
}
}};
+def template RegRegImmImmOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+ protected:
+ public:
+ // Constructor
+ %(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest, IntRegIndex _op1,
+ uint32_t _imm1, uint32_t _imm2);
+ %(BasicExecDeclare)s
+};
+}};
+
+def template RegRegImmImmOpConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ IntRegIndex _dest,
+ IntRegIndex _op1,
+ uint32_t _imm1,
+ uint32_t _imm2)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ _dest, _op1, _imm1, _imm2)
+ {
+ %(constructor)s;
+ }
+}};
+
def template RegImmRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{