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author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-29 02:04:34 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-29 02:04:34 -0800 |
commit | dc0e629ea1f074691d307cde3ab7dd51a5e2102f (patch) | |
tree | 9ce01152dc0c5231748a2da03199096a87ec34f5 /src/arch/arm | |
parent | 22a076a6d5b949db5595bbca530fe7db927f6367 (diff) | |
download | gem5-dc0e629ea1f074691d307cde3ab7dd51a5e2102f.tar.xz |
Implement Ali's review feedback.
Try to decrease indentation, and remove some redundant FullSystem checks.
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/faults.cc | 65 | ||||
-rw-r--r-- | src/arch/arm/tlb.cc | 20 | ||||
-rw-r--r-- | src/arch/arm/utility.cc | 78 |
3 files changed, 81 insertions, 82 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 52441e03f..061392f59 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -178,19 +178,20 @@ UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) { if (FullSystem) { ArmFault::invoke(tc, inst); + return; + } + + // If the mnemonic isn't defined this has to be an unknown instruction. + assert(unknown || mnemonic != NULL); + if (disabled) { + panic("Attempted to execute disabled instruction " + "'%s' (inst 0x%08x)", mnemonic, machInst); + } else if (unknown) { + panic("Attempted to execute unknown instruction (inst 0x%08x)", + machInst); } else { - // If the mnemonic isn't defined this has to be an unknown instruction. - assert(unknown || mnemonic != NULL); - if (disabled) { - panic("Attempted to execute disabled instruction " - "'%s' (inst 0x%08x)", mnemonic, machInst); - } else if (unknown) { - panic("Attempted to execute unknown instruction (inst 0x%08x)", - machInst); - } else { - panic("Attempted to execute unimplemented instruction " - "'%s' (inst 0x%08x)", mnemonic, machInst); - } + panic("Attempted to execute unimplemented instruction " + "'%s' (inst 0x%08x)", mnemonic, machInst); } } @@ -199,19 +200,20 @@ SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst) { if (FullSystem) { ArmFault::invoke(tc, inst); - } else { - // As of now, there isn't a 32 bit thumb version of this instruction. - assert(!machInst.bigThumb); - uint32_t callNum; - callNum = tc->readIntReg(INTREG_R7); - tc->syscall(callNum); - - // Advance the PC since that won't happen automatically. - PCState pc = tc->pcState(); - assert(inst); - inst->advancePC(pc); - tc->pcState(pc); + return; } + + // As of now, there isn't a 32 bit thumb version of this instruction. + assert(!machInst.bigThumb); + uint32_t callNum; + callNum = tc->readIntReg(INTREG_R7); + tc->syscall(callNum); + + // Advance the PC since that won't happen automatically. + PCState pc = tc->pcState(); + assert(inst); + inst->advancePC(pc); + tc->pcState(pc); } template<class T> @@ -252,13 +254,14 @@ template void AbortFault<DataAbort>::invoke(ThreadContext *tc, void ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) { DPRINTF(Faults, "Invoking ArmSev Fault\n"); - if (FullSystem) { - // Set sev_mailbox to 1, clear the pending interrupt from remote - // SEV execution and let pipeline continue as pcState is still - // valid. - tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); - tc->getCpuPtr()->clearInterrupt(INT_SEV, 0); - } + if (!FullSystem) + return; + + // Set sev_mailbox to 1, clear the pending interrupt from remote + // SEV execution and let pipeline continue as pcState is still + // valid. + tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); + tc->getCpuPtr()->clearInterrupt(INT_SEV, 0); } // return via SUBS pc, lr, xxx; rfe, movs, ldm diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 6953090d0..b19ad5265 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -418,14 +418,12 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, } } - if (!FullSystem) { - Addr paddr; - Process *p = tc->getProcessPtr(); + Addr paddr; + Process *p = tc->getProcessPtr(); - if (!p->pTable->translate(vaddr, paddr)) - return Fault(new GenericPageTableFault(vaddr)); - req->setPaddr(paddr); - } + if (!p->pTable->translate(vaddr, paddr)) + return Fault(new GenericPageTableFault(vaddr)); + req->setPaddr(paddr); return NoFault; } @@ -570,11 +568,9 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, } } - if (FullSystem) { - if (!bootUncacheability && - ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) - req->setFlags(Request::UNCACHEABLE); - } + if (!bootUncacheability && + ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) + req->setFlags(Request::UNCACHEABLE); switch ( (dacr >> (te->domain * 2)) & 0x3) { case 0: diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 42b5be181..ac81c7db6 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -63,48 +63,48 @@ initCPU(ThreadContext *tc, int cpuId) uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) { - if (FullSystem) { - if (size == (uint16_t)(-1)) - size = ArmISA::MachineBytes; - if (fp) - panic("getArgument(): Floating point arguments not implemented\n"); - - if (number < NumArgumentRegs) { - // If the argument is 64 bits, it must be in an even regiser - // number. Increment the number here if it isn't even. - if (size == sizeof(uint64_t)) { - if ((number % 2) != 0) - number++; - // Read the two halves of the data. Number is inc here to - // get the second half of the 64 bit reg. - uint64_t tmp; - tmp = tc->readIntReg(number++); - tmp |= tc->readIntReg(number) << 32; - return tmp; - } else { - return tc->readIntReg(number); - } - } else { - Addr sp = tc->readIntReg(StackPointerReg); - FSTranslatingPortProxy* vp = tc->getVirtProxy(); - uint64_t arg; - if (size == sizeof(uint64_t)) { - // If the argument is even it must be aligned - if ((number % 2) != 0) - number++; - arg = vp->read<uint64_t>(sp + - (number-NumArgumentRegs) * sizeof(uint32_t)); - // since two 32 bit args == 1 64 bit arg, increment number + if (!FullSystem) { + panic("getArgument() only implemented for full system mode.\n"); + M5_DUMMY_RETURN + } + + if (size == (uint16_t)(-1)) + size = ArmISA::MachineBytes; + if (fp) + panic("getArgument(): Floating point arguments not implemented\n"); + + if (number < NumArgumentRegs) { + // If the argument is 64 bits, it must be in an even regiser + // number. Increment the number here if it isn't even. + if (size == sizeof(uint64_t)) { + if ((number % 2) != 0) number++; - } else { - arg = vp->read<uint32_t>(sp + - (number-NumArgumentRegs) * sizeof(uint32_t)); - } - return arg; + // Read the two halves of the data. Number is inc here to + // get the second half of the 64 bit reg. + uint64_t tmp; + tmp = tc->readIntReg(number++); + tmp |= tc->readIntReg(number) << 32; + return tmp; + } else { + return tc->readIntReg(number); } } else { - panic("getArgument() only implemented for full system mode.\n"); - M5_DUMMY_RETURN + Addr sp = tc->readIntReg(StackPointerReg); + FSTranslatingPortProxy* vp = tc->getVirtProxy(); + uint64_t arg; + if (size == sizeof(uint64_t)) { + // If the argument is even it must be aligned + if ((number % 2) != 0) + number++; + arg = vp->read<uint64_t>(sp + + (number-NumArgumentRegs) * sizeof(uint32_t)); + // since two 32 bit args == 1 64 bit arg, increment number + number++; + } else { + arg = vp->read<uint32_t>(sp + + (number-NumArgumentRegs) * sizeof(uint32_t)); + } + return arg; } } |