diff options
author | Nathan Binkert <nate@binkert.org> | 2011-04-15 10:44:32 -0700 |
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committer | Nathan Binkert <nate@binkert.org> | 2011-04-15 10:44:32 -0700 |
commit | eddac53ff60c579eff28134bde84783fe36d6214 (patch) | |
tree | 9095c6b64a6fdabf4e0d00b2c8f2ca40ad495f49 /src/arch/arm | |
parent | f946d7bcdb4d0b4327857d319dd4ecdd1c320d62 (diff) | |
download | gem5-eddac53ff60c579eff28134bde84783fe36d6214.tar.xz |
trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/faults.cc | 1 | ||||
-rw-r--r-- | src/arch/arm/isa.cc | 2 | ||||
-rw-r--r-- | src/arch/arm/isa.hh | 1 | ||||
-rw-r--r-- | src/arch/arm/isa/includes.isa | 1 | ||||
-rw-r--r-- | src/arch/arm/nativetrace.cc | 1 | ||||
-rw-r--r-- | src/arch/arm/predecoder.cc | 1 | ||||
-rw-r--r-- | src/arch/arm/process.cc | 1 | ||||
-rw-r--r-- | src/arch/arm/remote_gdb.cc | 2 | ||||
-rw-r--r-- | src/arch/arm/stacktrace.hh | 1 | ||||
-rw-r--r-- | src/arch/arm/tlb.cc | 3 | ||||
-rw-r--r-- | src/arch/arm/types.hh | 1 |
11 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 4150adba6..03a65ea88 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -46,6 +46,7 @@ #include "base/trace.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" +#include "debug/Faults.hh" namespace ArmISA { diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 9988d431a..f7334ca9b 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -39,6 +39,8 @@ */ #include "arch/arm/isa.hh" +#include "debug/Arm.hh" +#include "debug/MiscRegs.hh" #include "sim/faults.hh" #include "sim/stat_control.hh" diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 88d08e971..48840bf07 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -46,6 +46,7 @@ #include "arch/arm/registers.hh" #include "arch/arm/tlb.hh" #include "arch/arm/types.hh" +#include "debug/Checkpoint.hh" class ThreadContext; class Checkpoint; diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa index aebce0944..b54545e10 100644 --- a/src/arch/arm/isa/includes.isa +++ b/src/arch/arm/isa/includes.isa @@ -87,6 +87,7 @@ output exec {{ #endif #include "base/cp_annotate.hh" +#include "debug/Arm.hh" #include "mem/packet.hh" #include "mem/packet_access.hh" #include "sim/sim_exit.hh" diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc index 531a6ee2e..2dd225e80 100644 --- a/src/arch/arm/nativetrace.cc +++ b/src/arch/arm/nativetrace.cc @@ -44,6 +44,7 @@ #include "arch/arm/miscregs.hh" #include "arch/arm/nativetrace.hh" #include "cpu/thread_context.hh" +#include "debug/ExecRegDelta.hh" #include "params/ArmNativeTrace.hh" #include "sim/byteswap.hh" diff --git a/src/arch/arm/predecoder.cc b/src/arch/arm/predecoder.cc index b87ca622e..a221f4e30 100644 --- a/src/arch/arm/predecoder.cc +++ b/src/arch/arm/predecoder.cc @@ -46,6 +46,7 @@ #include "arch/arm/utility.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" +#include "debug/Predecoder.hh" namespace ArmISA { diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 61349192f..c3b02744e 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -48,6 +48,7 @@ #include "base/loader/object_file.hh" #include "base/misc.hh" #include "cpu/thread_context.hh" +#include "debug/Stack.hh" #include "mem/page_table.hh" #include "mem/translating_port.hh" #include "sim/byteswap.hh" diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc index 2a4680782..1303f6ffc 100644 --- a/src/arch/arm/remote_gdb.cc +++ b/src/arch/arm/remote_gdb.cc @@ -151,6 +151,8 @@ #include "cpu/static_inst.hh" #include "cpu/thread_context.hh" #include "cpu/thread_state.hh" +#include "debug/GDBAcc.hh" +#include "debug/GDBMisc.hh" #include "mem/page_table.hh" #include "mem/physical.hh" #include "mem/port.hh" diff --git a/src/arch/arm/stacktrace.hh b/src/arch/arm/stacktrace.hh index 05fdb9e78..f88ed352b 100644 --- a/src/arch/arm/stacktrace.hh +++ b/src/arch/arm/stacktrace.hh @@ -33,6 +33,7 @@ #include "base/trace.hh" #include "cpu/static_inst.hh" +#include "debug/Stack.hh" class ThreadContext; namespace ArmISA diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index ccbca3d9c..ca2b68b3b 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -53,6 +53,9 @@ #include "base/str.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" +#include "debug/Checkpoint.hh" +#include "debug/TLB.hh" +#include "debug/TLBVerbose.hh" #include "mem/page_table.hh" #include "params/ArmTLB.hh" #include "sim/process.hh" diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index 6bd449e3d..9e7c0ff7f 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -48,6 +48,7 @@ #include "base/hashmap.hh" #include "base/misc.hh" #include "base/types.hh" +#include "debug/Predecoder.hh" namespace ArmISA { |