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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2016-08-15 12:00:35 +0100 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2016-08-15 12:00:35 +0100 |
| commit | 698767e5384a664b3bad52c9b40d62daf0eabbfc (patch) | |
| tree | 2cb02cf387574c233367bfd6602b9ac271815384 /src/arch/arm | |
| parent | 608a37c844829715c2a15ef079f7dd8db428779b (diff) | |
| download | gem5-698767e5384a664b3bad52c9b40d62daf0eabbfc.tar.xz | |
cpu, arch: fix the type used for the request flags
Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa.cc | 4 | ||||
| -rw-r--r-- | src/arch/arm/tlb.cc | 11 |
2 files changed, 8 insertions, 7 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index fabbe0756..2ae0bd7dc 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1465,7 +1465,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_ATS1HR: case MISCREG_ATS1HW: { - unsigned flags = 0; + Request::Flags flags = 0; BaseTLB::Mode mode = BaseTLB::Read; TLB::ArmTranslationType tranType = TLB::NormalTran; Fault fault; @@ -1710,7 +1710,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_AT_S1E3W_Xt: { RequestPtr req = new Request; - unsigned flags = 0; + Request::Flags flags = 0; BaseTLB::Mode mode = BaseTLB::Read; TLB::ArmTranslationType tranType = TLB::NormalTran; Fault fault; diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index a19a609b7..6658657aa 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -64,6 +64,7 @@ #include "debug/TLB.hh" #include "debug/TLBVerbose.hh" #include "mem/page_table.hh" +#include "mem/request.hh" #include "params/ArmTLB.hh" #include "sim/full_system.hh" #include "sim/process.hh" @@ -555,7 +556,7 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); else vaddr = vaddr_tainted; - uint32_t flags = req->getFlags(); + Request::Flags flags = req->getFlags(); bool is_fetch = (mode == Execute); bool is_write = (mode == Write); @@ -588,7 +589,7 @@ Fault TLB::checkPermissions(TlbEntry *te, RequestPtr req, Mode mode) { Addr vaddr = req->getVaddr(); // 32-bit don't have to purify - uint32_t flags = req->getFlags(); + Request::Flags flags = req->getFlags(); bool is_fetch = (mode == Execute); bool is_write = (mode == Write); bool is_priv = isPriv && !(flags & UserMode); @@ -760,7 +761,7 @@ TLB::checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode, Addr vaddr_tainted = req->getVaddr(); Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); - uint32_t flags = req->getFlags(); + Request::Flags flags = req->getFlags(); bool is_fetch = (mode == Execute); bool is_write = (mode == Write); bool is_priv M5_VAR_USED = isPriv && !(flags & UserMode); @@ -967,7 +968,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr); else vaddr = vaddr_tainted; - uint32_t flags = req->getFlags(); + Request::Flags flags = req->getFlags(); bool is_fetch = (mode == Execute); bool is_write = (mode == Write); @@ -981,7 +982,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, isPriv, flags & UserMode, isSecure, tranType & S1S2NsTran); DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " - "flags %#x tranType 0x%x\n", vaddr_tainted, mode, isStage2, + "flags %#lx tranType 0x%x\n", vaddr_tainted, mode, isStage2, scr, sctlr, flags, tranType); if ((req->isInstFetch() && (!sctlr.i)) || |