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| author | Nathanael Premillieu <nathanael.premillieu@irisa.fr> | 2012-09-25 11:49:40 -0500 |
|---|---|---|
| committer | Nathanael Premillieu <nathanael.premillieu@irisa.fr> | 2012-09-25 11:49:40 -0500 |
| commit | bfffbb67976fc4a01185e36c8eaf755454cf19a5 (patch) | |
| tree | 5541f88f999312b4dd41379b01fd0585d0e0093f /src/arch/arm | |
| parent | 04ca96427c1c910f0bddb2403dec9ea517f3869b (diff) | |
| download | gem5-bfffbb67976fc4a01185e36c8eaf755454cf19a5.tar.xz | |
ARM: Inst writing to cntrlReg registers not set as control inst
Deletion of the fact that instructions that writes to registers of type
"cntrlReg" are not set as control instruction (flag IsControl not set).
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 62684f5af..64deef044 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -118,7 +118,7 @@ let {{ return ('IntReg', 'uw', idx, None, srtNormal) def cntrlReg(idx, id = srtNormal, type = 'uw'): - return ('ControlReg', type, idx, (None, None, 'IsControl'), id) + return ('ControlReg', type, idx, None, id) def cntrlRegNC(idx, id = srtNormal, type = 'uw'): return ('ControlReg', type, idx, None, id) |