Merge ARM into the head. ARM will compile but may not actually work.

10 files changed, 94 insertions, 99 deletions

diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 21253edef..fa9faaddf 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -34,25 +34,21 @@ from m5.params import *
 class ArmTLB(SimObject):
     abstract = True
     type = 'ArmTLB'
-    cxx_namespace = 'ArmISA'
-    cxx_class = 'TLB'
+    cxx_class = 'ArmISA::TLB'
     size = Param.Int("TLB size")
 
 class ArmDTB(ArmTLB):
     type = 'ArmDTB'
-    cxx_namespace = 'ArmISA'
-    cxx_class = 'DTB'
+    cxx_class = 'ArmISA::DTB'
     size = 64
 
 class ArmITB(ArmTLB):
     type = 'ArmITB'
-    cxx_namespace = 'ArmISA'
-    cxx_class = 'ITB'
+    cxx_class = 'ArmISA::ITB'
     size = 64
 
 class ArmUTB(ArmTLB):
     type = 'ArmUTB'
-    cxx_namespace = 'ArmISA'
-    cxx_class = 'UTB'
+    cxx_class = 'ArmISA::UTB'
     size = 64
 
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 253114ad1..cf07699ce 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -131,9 +131,6 @@ namespace ArmISA
     const int ZeroReg = NumIntArchRegs;
     const int AddrReg = ZeroReg + 1; // Used to generate address for uops
 
-    const int ArgumentReg[] = {0, 1, 2, 3};
-    const int NumArgumentRegs = sizeof(ArgumentReg)/ sizeof(const int);
-
     const int SyscallNumReg = ReturnValueReg;
     const int SyscallPseudoReturnReg = ReturnValueReg;
     const int SyscallSuccessReg = ReturnValueReg;
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index 6d3153063..46b2f9bee 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -49,7 +49,7 @@ static SyscallReturn
 unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
           ThreadContext *tc)
 {
-    TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0));
+    TypedBufferArg<Linux::utsname> name(process->getSyscallArg(tc, 0));
 
     strcpy(name->sysname, "Linux");
     strcpy(name->nodename, "m5.eecs.umich.edu");
@@ -79,7 +79,7 @@ SyscallDesc ArmLinuxProcess::syscallDescs[] = {
     /* 14 */ SyscallDesc("mknod", unimplementedFunc),
     /* 15 */ SyscallDesc("chmod", chmodFunc<ArmLinux>),
     /* 16 */ SyscallDesc("lchown", chownFunc),
-    /* 17 */ SyscallDesc("break", obreakFunc), //???
+    /* 17 */ SyscallDesc("break", brkFunc), //???
     /* 18 */ SyscallDesc("unused#18", unimplementedFunc), //???
     /* 19 */ SyscallDesc("lseek", lseekFunc),
     /* 20 */ SyscallDesc("getpid", getpidFunc),
@@ -107,7 +107,7 @@ SyscallDesc ArmLinuxProcess::syscallDescs[] = {
     /* 42 */ SyscallDesc("pipe", unimplementedFunc),
     /* 43 */ SyscallDesc("times", unimplementedFunc),
     /* 44 */ SyscallDesc("prof", unimplementedFunc),
-    /* 45 */ SyscallDesc("brk", obreakFunc),
+    /* 45 */ SyscallDesc("brk", brkFunc),
     /* 46 */ SyscallDesc("setgid", unimplementedFunc),
     /* 47 */ SyscallDesc("getgid", getgidFunc),
     /* 48 */ SyscallDesc("signal", ignoreFunc),
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 00ba414ba..365d5b22c 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -43,8 +43,7 @@
 using namespace std;
 using namespace ArmISA;
 
-ArmLiveProcess::ArmLiveProcess(LiveProcessParams * params,
-        ObjectFile *objFile)
+ArmLiveProcess::ArmLiveProcess(LiveProcessParams *params, ObjectFile *objFile)
     : LiveProcess(params, objFile)
 {
     stack_base = 0xc0000000L;
@@ -147,12 +146,35 @@ ArmLiveProcess::argsInit(int intSize, int pageSize)
     initVirtMem->writeBlob(0xffff0fe0, insns, 8);
     */
 
-    threadContexts[0]->setIntReg(ArgumentReg1, argc);
-    threadContexts[0]->setIntReg(ArgumentReg2, argv_array_base);
-    threadContexts[0]->setIntReg(StackPointerReg, stack_min);
+    ThreadContext *tc = system->getThreadContext(contextIds[0]);
+
+    tc->setIntReg(ArgumentReg1, argc);
+    tc->setIntReg(ArgumentReg2, argv_array_base);
+    tc->setIntReg(StackPointerReg, stack_min);
 
     Addr prog_entry = objFile->entryPoint();
-    threadContexts[0]->setPC(prog_entry);
-    threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
+    tc->setPC(prog_entry);
+    tc->setNextPC(prog_entry + sizeof(MachInst));
+}
+
+ArmISA::IntReg
+ArmLiveProcess::getSyscallArg(ThreadContext *tc, int i)
+{
+    assert(i < 4);
+    return tc->readIntReg(ArgumentReg0 + i);
 }
 
+void
+ArmLiveProcess::setSyscallArg(ThreadContext *tc,
+        int i, ArmISA::IntReg val)
+{
+    assert(i < 4);
+    tc->setIntReg(ArgumentReg0 + i, val);
+}
+
+void
+ArmLiveProcess::setSyscallReturn(ThreadContext *tc,
+        SyscallReturn return_value)
+{
+    tc->setIntReg(ReturnValueReg, return_value.value());
+}
diff --git a/src/arch/arm/process.hh b/src/arch/arm/process.hh
index b97f4b0d2..8954d3719 100644
--- a/src/arch/arm/process.hh
+++ b/src/arch/arm/process.hh
@@ -53,6 +53,9 @@ class ArmLiveProcess : public LiveProcess
   public:
     void argsInit(int intSize, int pageSize);
 
+    ArmISA::IntReg getSyscallArg(ThreadContext *tc, int i);
+    void setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val);
+    void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
 };
 
 #endif // __ARM_PROCESS_HH__
diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc
index 5de0b3076..a4d6e9a4a 100644
--- a/src/arch/arm/regfile/regfile.cc
+++ b/src/arch/arm/regfile/regfile.cc
@@ -55,7 +55,7 @@ MiscRegFile::copyMiscRegs(ThreadContext *tc)
 }
 
 void
-RegFile::serialize(std::ostream &os)
+RegFile::serialize(EventManager *em, ostream &os)
 {
     intRegFile.serialize(os);
     //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
@@ -69,7 +69,7 @@ RegFile::serialize(std::ostream &os)
 }
 
 void
-RegFile::unserialize(Checkpoint *cp, const std::string &section)
+RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
     //UNSERIALIZE_ARRAY(floatRegFile);
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh
index 86799f18d..7f4d21353 100644
--- a/src/arch/arm/regfile/regfile.hh
+++ b/src/arch/arm/regfile/regfile.hh
@@ -38,11 +38,13 @@
 #include "sim/faults.hh"
 
 class Checkpoint;
+class EventManager;
 class ThreadContext;
 
 namespace ArmISA
 {
-    class RegFile {
+    class RegFile
+    {
       protected:
         IntRegFile intRegFile;		// (signed) integer register file
         FloatRegFile floatRegFile;	// floating point register file
@@ -176,8 +178,9 @@ namespace ArmISA
             //nnpc = val;
         }
 
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
+        void serialize(EventManager *em, std::ostream &os);
+        void unserialize(EventManager *em, Checkpoint *cp,
+                         const std::string &section);
 
         void changeContext(RegContextParam param, RegContextVal val)
         {
diff --git a/src/arch/arm/syscallreturn.hh b/src/arch/arm/syscallreturn.hh
deleted file mode 100644
index ad46c2232..000000000
--- a/src/arch/arm/syscallreturn.hh
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * Copyright (c) 2007-2008 The Florida State University
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- *          Korey Sewell
- *          Stephen Hines
- */
-
-#ifndef __ARCH_ARM_SYSCALLRETURN_HH__
-#define __ARCH_ARM_SYSCALLRETURN_HH__
-
-#include "sim/syscallreturn.hh"
-#include "cpu/thread_context.hh"
-
-namespace ArmISA
-{
-    static inline void setSyscallReturn(SyscallReturn return_value,
-            ThreadContext *tc)
-    {
-        if (return_value.successful()) {
-            // no error
-            //regs->setIntReg(SyscallSuccessReg, 0);
-            tc->setIntReg(ReturnValueReg, return_value.value());
-        } else {
-            // got an error, return details
-            //regs->setIntReg(SyscallSuccessReg, (IntReg) -1);
-            tc->setIntReg(ReturnValueReg, return_value.value());
-        }
-    }
-}
-
-#endif
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index d0cc57a1d..78eebddfe 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -29,6 +29,7 @@
  *
  * Authors: Nathan Binkert
  *          Steve Reinhardt
+ *          Jaidev Patwardhan
  *          Stephen Hines
  */
 
@@ -149,7 +150,7 @@ TLB::checkCacheability(RequestPtr &req)
   // or by the TLB entry
   if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
     // mark request as uncacheable
-    req->setFlags(req->getFlags() | UNCACHEABLE);
+    req->setFlags(req->getFlags() | Request::UNCACHEABLE);
   }
   return NoFault;
 }
@@ -278,7 +279,7 @@ TLB::regStats()
 }
 
 Fault
-ITB::translate(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
 {
 #if !FULL_SYSTEM
     Process * p = tc->getProcessPtr();
@@ -293,8 +294,17 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
 #endif
 }
 
+void
+ITB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation)
+{
+    assert(translation);
+    translation->finish(translateAtomic(req, tc), req, tc, false);
+}
+
+
 Fault
-DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
 {
 #if !FULL_SYSTEM
     Process * p = tc->getProcessPtr();
@@ -309,6 +319,14 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 #endif
 }
 
+void
+DTB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation, bool write)
+{
+    assert(translation);
+    translation->finish(translateAtomic(req, tc, write), req, tc, write);
+}
+
 ///////////////////////////////////////////////////////////////////////
 //
 //  Arm ITB
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 59fe1a60d..fea317ef3 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -62,6 +62,12 @@ struct TlbEntry
     TlbEntry() {}
     TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
 
+    void
+    updateVaddr(Addr new_vaddr)
+    {
+        panic("unimplemented");
+    }
+
     Addr pageStart()
     {
         return _pageStart;
@@ -92,14 +98,14 @@ class TLB : public BaseTLB
     void nextnlu() { if (++nlu >= size) nlu = 0; }
     ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const;
 
-    mutable Stats::Scalar<> read_hits;
-    mutable Stats::Scalar<> read_misses;
-    mutable Stats::Scalar<> read_acv;
-    mutable Stats::Scalar<> read_accesses;
-    mutable Stats::Scalar<> write_hits;
-    mutable Stats::Scalar<> write_misses;
-    mutable Stats::Scalar<> write_acv;
-    mutable Stats::Scalar<> write_accesses;
+    mutable Stats::Scalar read_hits;
+    mutable Stats::Scalar read_misses;
+    mutable Stats::Scalar read_acv;
+    mutable Stats::Scalar read_accesses;
+    mutable Stats::Scalar write_hits;
+    mutable Stats::Scalar write_misses;
+    mutable Stats::Scalar write_acv;
+    mutable Stats::Scalar write_accesses;
     Stats::Formula hits;
     Stats::Formula misses;
     Stats::Formula invalids;
@@ -136,23 +142,30 @@ class TLB : public BaseTLB
     void regStats();
 };
 
-class ITB : public TLB {
+class ITB : public TLB
+{
   public:
     typedef ArmTLBParams Params;
     ITB(const Params *p);
 
-    Fault translate(RequestPtr &req, ThreadContext *tc);
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation);
 };
 
-class DTB : public TLB {
+class DTB : public TLB
+{
   public:
     typedef ArmTLBParams Params;
     DTB(const Params *p);
 
-    Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation, bool write);
 };
 
-class UTB : public ITB, public DTB {
+class UTB : public ITB, public DTB
+{
   public:
     typedef ArmTLBParams Params;
     UTB(const Params *p);