ARM: Fix when the flag bits are updated for thumb.

1 files changed, 30 insertions, 29 deletions

diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 09433b824..3643fa88f 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -168,30 +168,30 @@ def format Thumb16ShiftAddSubMoveCmp() {{
         const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
         switch (bits(machInst, 13, 11)) {
           case 0x0: // lsl
-            return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
+            return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
           case 0x1: // lsr
-            return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
+            return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
           case 0x2: // asr
-            return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
+            return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
           case 0x3:
             switch (bits(machInst, 10, 9)) {
               case 0x0:
-                return new AddReg(machInst, rd, rn, rm, 0, LSL);
+                return new AddRegCc(machInst, rd, rn, rm, 0, LSL);
               case 0x1:
-                return new SubReg(machInst, rd, rn, rm, 0, LSL);
+                return new SubRegCc(machInst, rd, rn, rm, 0, LSL);
               case 0x2:
-                return new AddImm(machInst, rd, rn, imm3, true);
+                return new AddImmCc(machInst, rd, rn, imm3, true);
               case 0x3:
-                return new SubImm(machInst, rd, rn, imm3, true);
+                return new SubImmCc(machInst, rd, rn, imm3, true);
             }
           case 0x4:
-            return new MovImm(machInst, rd8, INTREG_ZERO, imm8, true);
+            return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false);
           case 0x5:
             return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
           case 0x6:
-            return new AddImm(machInst, rd8, rd8, imm8, true);
+            return new AddImmCc(machInst, rd8, rd8, imm8, true);
           case 0x7:
-            return new SubImm(machInst, rd8, rd8, imm8, true);
+            return new SubImmCc(machInst, rd8, rd8, imm8, true);
         }
     }
     '''
@@ -204,37 +204,37 @@ def format Thumb16DataProcessing() {{
         const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
         switch (bits(machInst, 9, 6)) {
           case 0x0:
-            return new AndReg(machInst, rdn, rdn, rm, 0, LSL);
+            return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL);
           case 0x1:
-            return new EorReg(machInst, rdn, rdn, rm, 0, LSL);
+            return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL);
           case 0x2: //lsl
-            return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSL);
+            return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL);
           case 0x3: //lsr
-            return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSR);
+            return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR);
           case 0x4: //asr
-            return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ASR);
+            return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR);
           case 0x5:
-            return new AdcReg(machInst, rdn, rdn, rm, 0, LSL);
+            return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL);
           case 0x6:
-            return new SbcReg(machInst, rdn, rdn, rm, 0, LSL);
+            return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL);
           case 0x7: // ror
-            return new MovRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ROR);
+            return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR);
           case 0x8:
-            return new TstReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
+            return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
           case 0x9:
-            return new RsbImm(machInst, rdn, rm, 0, true);
+            return new RsbImmCc(machInst, rdn, rm, 0, true);
           case 0xa:
-            return new CmpReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
+            return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
           case 0xb:
-            return new CmnReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
+            return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
           case 0xc:
-            return new OrrReg(machInst, rdn, rdn, rm, 0, LSL);
+            return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL);
           case 0xd:
-            return new Mul(machInst, rdn, rm, rdn);
+            return new MulCc(machInst, rdn, rm, rdn);
           case 0xe:
-            return new BicReg(machInst, rdn, rdn, rm, 0, LSL);
+            return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL);
           case 0xf:
-            return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
+            return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
         }
     }
     '''
@@ -251,7 +251,7 @@ def format Thumb16SpecDataAndBx() {{
           case 0x0:
             return new AddReg(machInst, rdn, rdn, rm, 0, LSL);
           case 0x1:
-            return new CmpReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
+            return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
           case 0x2:
             return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
           case 0x3:
@@ -392,10 +392,10 @@ def format Thumb32DataProcModImm() {{
         return '''
             if (s) {
                 return new %(mnem)sImmCc(machInst, %(dest)s,
-                                          %(op1)s, imm, true);
+                                          %(op1)s, imm, rotC);
             } else {
                 return new %(mnem)sImm(machInst, %(dest)s,
-                                        %(op1)s, imm, true);
+                                        %(op1)s, imm, rotC);
             }
         ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
 
@@ -407,6 +407,7 @@ def format Thumb32DataProcModImm() {{
         const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
         const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 |
                                  bits(machInst, 14, 12);
+        const bool rotC = ctrlImm > 3;
         const uint32_t dataImm = bits(machInst, 7, 0);
         const uint32_t imm = modified_imm(ctrlImm, dataImm);
         switch (op) {