ARM, Simple CPU: Fix an index and add assert checks.

2 files changed, 10 insertions, 10 deletions

diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 6f5e17497..d670d673d 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -33,6 +33,7 @@
 #ifndef __ARCH_ARM_ISA_TRAITS_HH__
 #define __ARCH_ARM_ISA_TRAITS_HH__
 
+#include "arch/arm/max_inst_regs.hh"
 #include "arch/arm/types.hh"
 #include "base/types.hh"
 
@@ -45,6 +46,8 @@ class StaticInstPtr;
 namespace ArmISA
 {
     using namespace LittleEndianGuest;
+    using ArmISAInst::MaxInstSrcRegs;
+    using ArmISAInst::MaxInstDestRegs;
 
     StaticInstPtr decodeInst(ExtMachInst);
 
@@ -100,20 +103,10 @@ namespace ArmISA
     const int NumIntSpecialRegs = 19;
     const int NumFloatArchRegs = 16;
     const int NumFloatSpecialRegs = 5;
-    const int NumControlRegs = 7;
     const int NumInternalProcRegs = 0;
 
     const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
     const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
-    const int NumMiscRegs = NumControlRegs;
-
-    const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-
-    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-
-    // Static instruction parameters
-    const int MaxInstSrcRegs = 5;
-    const int MaxInstDestRegs = 3;
 
     // semantically meaningful register indices
     const int ReturnValueReg = 0;
diff --git a/src/arch/arm/regfile/misc_regfile.hh b/src/arch/arm/regfile/misc_regfile.hh
index eda0e8f05..c2b2f39d7 100644
--- a/src/arch/arm/regfile/misc_regfile.hh
+++ b/src/arch/arm/regfile/misc_regfile.hh
@@ -32,6 +32,7 @@
 #define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
 
 #include "arch/arm/isa_traits.hh"
+#include "arch/arm/miscregs.hh"
 #include "arch/arm/types.hh"
 #include "sim/faults.hh"
 
@@ -39,6 +40,8 @@ class ThreadContext;
 
 namespace ArmISA
 {
+    const int NumMiscRegs = NUM_MISCREGS;
+
     static inline std::string getMiscRegName(RegIndex)
     {
         return "";
@@ -59,22 +62,26 @@ namespace ArmISA
 
         MiscReg readRegNoEffect(int misc_reg)
         {
+            assert(misc_reg < NumMiscRegs);
             return miscRegFile[misc_reg];
         }
 
         MiscReg readReg(int misc_reg, ThreadContext *tc)
         {
+            assert(misc_reg < NumMiscRegs);
             return miscRegFile[misc_reg];
         }
 
         void setRegNoEffect(int misc_reg, const MiscReg &val)
         {
+            assert(misc_reg < NumMiscRegs);
             miscRegFile[misc_reg] = val;
         }
 
         void setReg(int misc_reg, const MiscReg &val,
                                ThreadContext *tc)
         {
+            assert(misc_reg < NumMiscRegs);
             miscRegFile[misc_reg] = val;
         }