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author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-07 02:10:34 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-07 02:10:34 -0800 |
commit | 36a822f08e88483b41af214ace4fd3dccf3aa8cb (patch) | |
tree | d7c4c08590459d967a1d7638b02c586911826953 /src/arch/arm | |
parent | 85424bef192c02a47c0d46c2d99ac0a5d6e55a99 (diff) | |
parent | f171a29118e1d80c04c72d2fb5f024fed4fb62af (diff) | |
download | gem5-36a822f08e88483b41af214ace4fd3dccf3aa8cb.tar.xz |
Merge with main repository.
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/isa/formats/fp.isa | 18 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/fp.isa | 4 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/macromem.isa | 7 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/neon.isa | 16 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/mem.isa | 4 | ||||
-rw-r--r-- | src/arch/arm/linux/linux.hh | 1 | ||||
-rw-r--r-- | src/arch/arm/linux/process.cc | 2 | ||||
-rw-r--r-- | src/arch/arm/process.cc | 3 |
8 files changed, 28 insertions, 27 deletions
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index 812338c30..0cb27d7f1 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -561,20 +561,22 @@ let {{ } } case 0xa: + if (q) + return new Unknown(machInst); if (b) { - return decodeNeonUSThreeReg<VpminD, VpminQ>( - q, u, size, machInst, vd, vn, vm); + return decodeNeonUSThreeUSReg<VpminD>( + u, size, machInst, vd, vn, vm); } else { - return decodeNeonUSThreeReg<VpmaxD, VpmaxQ>( - q, u, size, machInst, vd, vn, vm); + return decodeNeonUSThreeUSReg<VpmaxD>( + u, size, machInst, vd, vn, vm); } case 0xb: if (b) { - if (u) { + if (u || q) { return new Unknown(machInst); } else { - return decodeNeonUThreeReg<NVpaddD, NVpaddQ>( - q, size, machInst, vd, vn, vm); + return decodeNeonUThreeUSReg<NVpaddD>( + size, machInst, vd, vn, vm); } } else { if (u) { @@ -1542,7 +1544,7 @@ let {{ else return new NVswpD<uint64_t>(machInst, vd, vm); case 0x1: - return decodeNeonUTwoMiscReg<NVtrnD, NVtrnQ>( + return decodeNeonUTwoMiscSReg<NVtrnD, NVtrnQ>( q, size, machInst, vd, vm); case 0x2: return decodeNeonUTwoMiscReg<NVuzpD, NVuzpQ>( diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index f82858bbd..b701995f4 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -447,7 +447,7 @@ let {{ exec_output = "" singleSimpleCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = (FPSCR) FpscrExc; + FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; FpDest = %(op)s; ''' singleCode = singleSimpleCode + ''' @@ -457,7 +457,7 @@ let {{ "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)" singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)" doubleCode = vfpEnabledCheckCode + ''' - FPSCR fpscr = (FPSCR) FpscrExc; + FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc; double dest = %(op)s; FpDestP0_uw = dblLow(dest); FpDestP1_uw = dblHi(dest); diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 815d4c258..db36a3fff 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -563,15 +563,16 @@ let {{ let {{ exec_output = '' - for type in ('uint8_t', 'uint16_t', 'uint32_t'): + for typeSize in (8, 16, 32): for sRegs in 1, 2: - for dRegs in range(sRegs, 5): + for dRegs in range(sRegs, min(sRegs * 64 / typeSize + 1, 5)): for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop", "MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop", "MicroPackNeon%(dRegs)dto%(sRegs)dUop"): Name = format % { "sRegs" : sRegs * 2, "dRegs" : dRegs * 2 } - substDict = { "class_name" : Name, "targs" : type } + substDict = { "class_name" : Name, + "targs" : "uint%d_t" % typeSize } exec_output += MicroNeonExecDeclare.subst(substDict) }}; diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index 9565ee14a..b1ad1eeb3 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -1616,10 +1616,8 @@ let {{ threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", unsignedTypes, 2, vaddCode) threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", unsignedTypes, 4, vaddCode) - threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", unsignedTypes, + threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", smallUnsignedTypes, 2, vaddCode, pairwise=True) - threeEqualRegInst("vpadd", "NVpaddQ", "SimdAddOp", unsignedTypes, - 4, vaddCode, pairwise=True) vaddlwCode = ''' destElem = (BigElement)srcElem1 + (BigElement)srcElem2; ''' @@ -2110,11 +2108,9 @@ let {{ ''' threeRegLongInst("vmull", "Vmullp", "SimdMultOp", smallUnsignedTypes, vmullpCode) - threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", allTypes, 2, vmaxCode, pairwise=True) - threeEqualRegInst("vpmax", "VpmaxQ", "SimdCmpOp", allTypes, 4, vmaxCode, pairwise=True) + threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, vmaxCode, pairwise=True) - threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", allTypes, 2, vminCode, pairwise=True) - threeEqualRegInst("vpmin", "VpminQ", "SimdCmpOp", allTypes, 4, vminCode, pairwise=True) + threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True) vqdmulhCode = ''' FPSCR fpscr = (FPSCR) FpscrQc; @@ -3137,8 +3133,10 @@ let {{ destReg.elements[i + 1] = mid; } ''' - twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", unsignedTypes, 2, vtrnCode) - twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", unsignedTypes, 4, vtrnCode) + twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", + smallUnsignedTypes, 2, vtrnCode) + twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", + smallUnsignedTypes, 4, vtrnCode) vuzpCode = ''' Element mid[eCount]; diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index a00114409..a4a740f89 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -1112,7 +1112,7 @@ def template LoadRegConstructor {{ (IntRegIndex)_index) { %(constructor)s; - bool conditional = false; + bool conditional M5_VAR_USED = false; if (!(condCode == COND_AL || condCode == COND_UC)) { conditional = true; for (int x = 0; x < _numDestRegs; x++) { @@ -1166,7 +1166,7 @@ def template LoadImmConstructor {{ (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) { %(constructor)s; - bool conditional = false; + bool conditional M5_VAR_USED = false; if (!(condCode == COND_AL || condCode == COND_UC)) { conditional = true; for (int x = 0; x < _numDestRegs; x++) { diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh index 33e48fc93..40d586aaf 100644 --- a/src/arch/arm/linux/linux.hh +++ b/src/arch/arm/linux/linux.hh @@ -91,6 +91,7 @@ class ArmLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; //@{ /// For getrusage(). diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc index f17749252..c65962d00 100644 --- a/src/arch/arm/linux/process.cc +++ b/src/arch/arm/linux/process.cc @@ -503,7 +503,7 @@ void ArmLinuxProcess::initState() { ArmLiveProcess::initState(); - pTable->allocate(commPage, PageBytes); + allocateMem(commPage, PageBytes); ThreadContext *tc = system->getThreadContext(contextIds[0]); uint8_t swiNeg1[] = { diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index c3b02744e..aa5d7dfce 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -251,8 +251,7 @@ ArmLiveProcess::argsInit(int intSize, int pageSize) stack_size = stack_base - stack_min; // map memory - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents uint32_t sentry_base = stack_base - sentry_size; |