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authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2015-05-05 03:22:34 -0400
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2015-05-05 03:22:34 -0400
commit706597f021811511e71fddeeab7dcfc33bfd5f35 (patch)
tree3967d475572bc0e380ee430eec9035ba35b0d216 /src/arch/arm
parent48281375ee23283d24cf9d7fe5f6315afdb3a6fc (diff)
downloadgem5-706597f021811511e71fddeeab7dcfc33bfd5f35.tar.xz
arm: Relax ordering for some uncacheable accesses
We currently assume that all uncacheable memory accesses are strictly ordered. Instead of always enforcing strict ordering, we now only enforce it if the required memory type is device memory or strongly ordered memory.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/tlb.cc8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 8c3bb047d..61c2eb9d6 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1076,7 +1076,13 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
setAttr(te->attributes);
if (te->nonCacheable)
- req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
+ req->setFlags(Request::UNCACHEABLE);
+
+ // Require requests to be ordered if the request goes to
+ // strongly ordered or device memory (i.e., anything other
+ // than normal memory requires strict order).
+ if (te->mtype != TlbEntry::MemoryType::Normal)
+ req->setFlags(Request::STRICT_ORDER);
Addr pa = te->pAddr(vaddr);
req->setPaddr(pa);