O3: Fix a few bugs in the TableWalker object.

Uncacheable requests were set as such only in atomic mode.
currState->delayed is checked in place of currState->timing for resetting
currState in atomic mode.

2 files changed, 19 insertions, 18 deletions

diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 6b2113639..e6dd728dd 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -208,19 +208,20 @@ TableWalker::processWalk()
         return f;
     }
 
+    Request::Flags flag = 0;
+    if (currState->sctlr.c == 0) {
+        flag = Request::UNCACHEABLE;
+    }
+
     if (currState->timing) {
         port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
                 &doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
-                currState->tc->getCpuPtr()->ticks(1));
+                currState->tc->getCpuPtr()->ticks(1), flag);
         DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
                 stateQueueL1.size());
         stateQueueL1.push_back(currState);
         currState = NULL;
     } else {
-        Request::Flags flag = 0;
-        if (currState->sctlr.c == 0){
-           flag = Request::UNCACHEABLE;
-        }
         port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
                 NULL, (uint8_t*)&currState->l1Desc.data,
                 currState->tc->getCpuPtr()->ticks(1), flag);
@@ -472,7 +473,7 @@ TableWalker::doL1Descriptor()
     switch (currState->l1Desc.type()) {
       case L1Descriptor::Ignore:
       case L1Descriptor::Reserved:
-        if (!currState->delayed) {
+        if (!currState->timing) {
             currState->tc = NULL;
             currState->req = NULL;
         }
@@ -577,7 +578,7 @@ TableWalker::doL2Descriptor()
 
     if (currState->l2Desc.invalid()) {
         DPRINTF(TLB, "L2 descriptor invalid, causing fault\n");
-        if (!currState->delayed) {
+        if (!currState->timing) {
             currState->tc = NULL;
             currState->req = NULL;
         }
@@ -622,7 +623,7 @@ TableWalker::doL2Descriptor()
     memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(),
              currState->l2Desc.shareable());
 
-    if (!currState->delayed) {
+    if (!currState->timing) {
         currState->tc = NULL;
         currState->req = NULL;
     }
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 267a7ad26..96a39cc61 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -93,14 +93,14 @@ class TableWalker : public MemObject
         {
             if (supersection())
                 panic("Super sections not implemented\n");
-            return mbits(data, 31,20);
+            return mbits(data, 31, 20);
         }
         /** Return the physcal address of the entry, bits in position*/
         Addr paddr(Addr va) const
         {
             if (supersection())
                 panic("Super sections not implemented\n");
-            return mbits(data, 31,20) | mbits(va, 20, 0);
+            return mbits(data, 31, 20) | mbits(va, 19, 0);
         }
 
 
@@ -109,7 +109,7 @@ class TableWalker : public MemObject
         {
             if (supersection())
                 panic("Super sections not implemented\n");
-            return bits(data, 31,20);
+            return bits(data, 31, 20);
         }
 
         /** Is the translation global (no asid used)? */
@@ -127,19 +127,19 @@ class TableWalker : public MemObject
         /** Three bit access protection flags */
         uint8_t ap() const
         {
-            return (bits(data, 15) << 2) | bits(data,11,10);
+            return (bits(data, 15) << 2) | bits(data, 11, 10);
         }
 
         /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
         uint8_t domain() const
         {
-            return bits(data,8,5);
+            return bits(data, 8, 5);
         }
 
         /** Address of L2 descriptor if it exists */
         Addr l2Addr() const
         {
-            return mbits(data, 31,10);
+            return mbits(data, 31, 10);
         }
 
         /** Memory region attributes: ARM DDI 0406B: B3-32.
@@ -149,7 +149,7 @@ class TableWalker : public MemObject
          */
         uint8_t texcb() const
         {
-            return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2;
+            return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2;
         }
 
         /** If the section is shareable. See texcb() comment. */
@@ -187,7 +187,7 @@ class TableWalker : public MemObject
         /** Is the entry invalid */
         bool invalid() const
         {
-            return bits(data, 1,0) == 0;;
+            return bits(data, 1, 0) == 0;
         }
 
         /** What is the size of the mapping? */
@@ -218,8 +218,8 @@ class TableWalker : public MemObject
         uint8_t texcb() const
         {
             return large() ?
-                (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 14, 12) << 2)) :
-                (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 8, 6) << 2));
+                (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) :
+                (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2));
         }
 
         /** Return the physical frame, bits shifted right */