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authorAli Saidi <ali.saidi@arm.com>2010-08-25 19:10:42 -0500
committerAli Saidi <ali.saidi@arm.com>2010-08-25 19:10:42 -0500
commitc2d5d2b53d1d3bfb83ce0cf0332f81c4ffea112f (patch)
treec8216cb9fe5a34c32307fd667163f03592c67f16 /src/arch/arm
parent99fafb72b87f3b63f205bee7b20b8c19724d6305 (diff)
downloadgem5-c2d5d2b53d1d3bfb83ce0cf0332f81c4ffea112f.tar.xz
ARM: Set the high bits in the part number so it's considered new by some code.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/isa.cc10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f5bbc3610..5655c1265 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -74,11 +74,11 @@ ISA::clear()
* Variant = 0,
*/
miscRegs[MISCREG_MIDR] =
- (0x35 << 24) | //Implementor is '5' from "M5"
- (0 << 20) | //Variant
- (0xf << 16) | //Architecture from CPUID scheme
- (0 << 4) | //Primary part number
- (0 << 0) | //Revision
+ (0x35 << 24) | // Implementor is '5' from "M5"
+ (0 << 20) | // Variant
+ (0xf << 16) | // Architecture from CPUID scheme
+ (0xf00 << 4) | // Primary part number
+ (0 << 0) | // Revision
0;
// Separate Instruction and Data TLBs.