diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-07-18 08:31:16 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-07-18 08:31:16 -0400 |
| commit | d4273cc9a6f3c00566e97ebcd71509ed14477b37 (patch) | |
| tree | 9b50625fc5d2bb457a959f379a45687903660237 /src/arch/arm | |
| parent | 4e8ecd7c6fd0447f563179b5a8fdbb13b562ca9e (diff) | |
| download | gem5-d4273cc9a6f3c00566e97ebcd71509ed14477b37.tar.xz | |
mem: Set the cache line size on a system level
This patch removes the notion of a peer block size and instead sets
the cache line size on the system level.
Previously the size was set per cache, and communicated through the
interconnect. There were plenty checks to ensure that everyone had the
same size specified, and these checks are now removed. Another benefit
that is not yet harnessed is that the cache line size is now known at
construction time, rather than after the port binding. Hence, the
block size can be locally stored and does not have to be queried every
time it is used.
A follow-on patch updates the configuration scripts accordingly.
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 117873450..2b67e6cf6 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012 ARM Limited + * Copyright (c) 2010-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -238,7 +238,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) //all caches have the same line size in gem5 //4 byte words in ARM unsigned lineSizeWords = - tc->getCpuPtr()->getInstPort().peerBlockSize() / 4; + tc->getSystemPtr()->cacheLineSize() / 4; unsigned log2LineSizeWords = 0; while (lineSizeWords >>= 1) { |