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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-11-02 10:33:30 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-11-07 15:22:43 +0000
commit07a2fd7ec2fbcd7fcb0b10968dc9c738d67adda2 (patch)
treef78a23d35d85c863a93f9c27235fb12921dbe5c6 /src/arch/arm
parent46a79f7d10f7b8eabd4e3bb45ff50959d04a2571 (diff)
downloadgem5-07a2fd7ec2fbcd7fcb0b10968dc9c738d67adda2.tar.xz
arch-arm: Remove SCTLR.VE bit
ARMv8 has removed SCTLR.VE bit which is now hardcoded to 0. We are removing it from gem5 since we were not handling it anyway. Change-Id: Ibde2db45c7f8add4a3188f2cb8c23701a6088d03 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13998 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/faults.cc5
-rw-r--r--src/arch/arm/miscregs_types.hh1
2 files changed, 1 insertions, 5 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index ab0d0de0f..bd06ea288 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -300,10 +300,6 @@ ArmFault::getVector(ThreadContext *tc)
// ARM ARM issue C B1.8.1
bool haveSecurity = ArmSystem::haveSecurity(tc);
- // panic if SCTLR.VE because I have no idea what to do with vectored
- // interrupts
- SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
- assert(!sctlr.ve);
// Check for invalid modes
CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
assert(haveSecurity || cpsr.mode != MODE_MON);
@@ -318,6 +314,7 @@ ArmFault::getVector(ThreadContext *tc)
base = tc->readMiscReg(MISCREG_HVBAR);
break;
default:
+ SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
if (sctlr.v) {
base = HighVecs;
} else {
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index 0a862360e..c3ee6ca00 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -319,7 +319,6 @@ namespace ArmISA
// DC CVAC and IC IVAU instructions
// (AArch64 SCTLR_EL1 only)
Bitfield<25> ee; // Exception Endianness
- Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
// (AArch64 SCTLR_EL1 only)
Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)